International Business Machines Corporation

Globalfoundries Inc.

Samsung Electronics Co., Ltd.

Globalfoundries U.S. 2 LLC

Toshiba America Electronic Components, Inc.

Globalfoundaries Inc.

Edward J Nowak

Brent A Anderson

Andres Bryant

Jed Hickory Rankin

William F Clark, Jr

John J Ellis-Monaghan

Richard Quimby Williams

Kerry Bernstein

Robert J Gauthier, Jr

Robert Russell Robison

William R Tonti

Randy William Mann

Jeffrey Scott Brown

Kangguo Cheng

James William Adkisson

Ruilong Xie

Jack Allan Mandelman

Steven H Voldman

Julien Frougier

Alvin Jose Joseph

Terence B Hook

Jeffrey Bowman Johnson

Matthew Joseph Breitwisch

Meikei Ieong

Norman Jay Rohrer

Steven J Holmes

Ramachandra Divakaruni

James Albert Slinkman

Hussein Ibrahim Hanafi

Bruce Bennett Doris

Ali Khakifirooz

Junli Wang

David V Horak

Chung H Lam

Jeffrey W Sleight

Kevin K Chan

Arne Watson Ballantine

Fee Li Lie

Kern Rim

Brian Joseph Greene

Omer H Dokumaci

John Joseph Pekarik

Joseph Andrew Iadanza

Yun Shi

Devendra K Sadana

Ghavam G Shahidi

Claude Louis Bertin

Mark Charles Hakey

Lars W Liebmann

Qizhi Liu

Herbert Lei Ho

Edmund Juris Sprogis

Robert K Leidy

John Edward Barth, Jr

Wilbur David Pricer

Tze-Chiang Chen

Wagdi William Abadeer

Jeanne P Bickford

Jason D Hibbeler

Jochen C Beintner

Howard L Kalter

Jeffrey P Gambino

Chanro Park

Rajiv V Joshi

Nicolas J Loubet

Toshiharu Furukawa

Josephine B Chang

Dureseti Chidambarrao

Shu-Jen Han

Mark David Jaffe

Kirk David Peterson

Michael Patrick Chudzik

Subramanian Srikanteswara Iyer

Shreesh Narasimha

Wilfried Haensch

Kenneth Joseph Goodnow

Daniel Chanemougame

Robert H Dennard

Stephen Victor Kosonocky

Huiming Bu

Bomy A Chen

Min Yang

Anthony Richard Bonaccio

Albert Manhee Chu

William Thomas Motsiff

Johnathan E Faltermeier

Christopher Stephen Putnam

Anthony K Stamper

Michael A Guillorn

Keith Kwong Hon Wong

Reinaldo Ariel Vega

Min Gyu Sung

Robert Mark Rassel

Frank David Ferraiolo

Siva P Adusumilli

Jagar Singh

David Louis Harame

Qiqing Christine Ouyang

Kevin John Nowka

James Stuart Dunn

A semiconductor structure includes a silicon-on-insulator (SOI) substrate, the SOI substrate comprising a bottom silicon layer, a buried oxide (BOX) layer, and a top silicon layer; a plurality of active devices formed on the top silicon layer; and an isolation region located between two of the active devices, wherein at least two of the plurality of active devices are electrically isolated from each other by the isolation region, and wherein the isolation region extends through the top silicon layer to the BOX layer.

Isolation region fabrication for replacement gate processing

Vertical field effect transistors (FETs) with minimum pitch and methods of manufacture are disclosed. The structure includes at least one vertical fin structure and gate material contacting with the at least one vertical fin structure. The structure further includes metal material in electrical contact with the ends of the at least one vertical fin.

Vertical field effect transistors

Embodiments of the present invention are directed to techniques for providing an novel field effect transistor (FET) architecture that includes a center fin region and one or more vertically stacked nanosheets. In a non-limiting embodiment of the invention, a nanosheet stack is formed over a substrate. The nanosheet stack can include one or more first semiconductor layers and one or more first sacrificial layers. A trench is formed by removing a portion of the one or more first semiconductor layers and the one or more first sacrificial layers. The trench exposes a surface of a bottommost sacrificial layer of the one or more first sacrificial layers. The trench can be filled with one or more second semiconductor layers and one or more second sacrificial layers such that each of the one or more second semiconductor layers is in contact with a sidewall of one of the one or more first semiconductor layers.

Transistor channel having vertically stacked nanosheets coupled by fin-shaped bridge regions

Embodiments of the present disclosure provide a neuromorphic circuit structure including: a first vertically-extending neural node configured to generate an output signal based on at least one input to the first vertically-extending neural node; an interconnect stack adjacent the vertically-extending neural node, the interconnect stack including a first conducting line coupled to the first vertically-extending neural node and configured to receive the output signal, a second conducting line vertically separated from the first conducting line, and a memory via vertically coupling the first conducting line to the second conducting line; and a second vertically-extending neural node adjacent the interconnect stack, and coupled to the second conducting line for receiving the output signal from the first vertically-extending neural node.

Neuromorphic circuit structure and method to form same

A vertical transport fin field effect transistor (VTFET) with a smaller cross-sectional area at the top of the fin than at the bottom, including, a substrate, a vertical fin on the substrate, wherein the vertical fin has a cross-sectional area at the base of the vertical fin that is larger than a cross-sectional area at the top of the vertical fin, wherein the cross-sectional area at the top of the vertical fin is in the range of about 10% to about 75% of the cross-sectional area at the base of the vertical fin, and a central gated region between the base and the top of the vertical fin.

Fabrication of a vertical field effect transistor device with a modified vertical fin geometry

Embodiments of the present invention are directed to techniques for providing an novel field effect transistor (FET) architecture that includes a center fin region and one or more vertically stacked nanosheets. In a non-limiting embodiment of the invention, a non-planar channel region is formed having a first semiconductor layer, a second semiconductor layer, and a fin-shaped bridge layer between the first semiconductor layer and the second semiconductor layer. Forming the non-planar channel region can include forming a nanosheet stack over a substrate, forming a trench by removing a portion of the nanosheet stack, and forming a third semiconductor layer in the trench. Outer surfaces of the first semiconductor layer, the second semiconductor layer, and the fin-shaped bridge region define an effective channel width of the non-planar channel region.

A method of forming a via and a wiring structure formed are disclosed. The method may include forming a conductive line in a first dielectric layer; forming a hard mask adjacent to the conductive line after the conductive line forming; forming a second dielectric layer over the hard mask; and forming a via opening to the conductive line in the second dielectric layer. The via opening lands at least partially on the hard mask to self-align the via opening to the conductive line. A via may be formed by filling the via opening with a conductor.

Self-aligned via forming to conductive line and related wiring structure

Structures for a memory cell and methods associated with forming and using such structures. The structure includes a silicon-on-insulator wafer including a device layer, a substrate, and a buried insulator layer between the device layer and the substrate. The structure further includes a field-effect transistor having first and second source/drain regions and a gate electrode that are over the buried insulator layer. A moat region is arranged in the substrate beneath the field-effect transistor, a well is arranged in the substrate beneath the moat region, and an isolation region extends through the device layer and the buried insulator layer into the substrate. The isolation region is arranged to surround a portion of the device layer defining an active region for the field-effect transistor and a portion of the moat region. A fence region, which extends between the well and the isolation region, surrounds the portion of the moat region.

Simplified memory cells based on fully-depleted silicon-on-insulator transistors

A semiconductor device including semiconductor material having a bend and a trench feature formed at the bend, and a gate structure at least partially disposed in the trench feature. A method of fabricating a semiconductor structure including forming a semiconductor material with a trench feature over a layer, forming a gate structure at least partially in the trench feature, and bending the semiconductor material such that stress is induced in the semiconductor material in an inversion channel region of the gate structure.

FINFET having a gate structure in a trench feature in a bent fin

The method includes prior to depositing a gate on a first vertical FET on a semiconductor substrate, depositing a first layer on the first vertical FET on the semiconductor substrate. The method further includes prior to depositing a gate on a second vertical FET on the semiconductor substrate, depositing a second layer on the second vertical FET on the semiconductor substrate. The method further includes etching the first layer on the first vertical FET to a lower height than the second layer on the second vertical FET. The method further includes depositing a gate material on both the first vertical FET and the second vertical FET. The method further includes etching the gate material on both the first vertical FET and the second vertical FET to a co-planar height.

Variable gate lengths for vertical transistors

Structures for switches and methods for forming structures that include a switch. A first well and a section well are arranged in a substrate. Trench isolation regions are arranged in the substrate to define multiple active device regions. Each of the active device regions includes a section of the first well that is surrounded by the trench isolation regions. The second well has an opposite conductivity type from the first well. The active device regions and the trench isolation regions are arranged between the top surface of the substrate and the second well, and the second well is contiguous with the trench isolation regions.

Isolation techniques for high-voltage device structures

The present disclosure relates to semiconductor structures and, more particularly, to virtual drains for decreased harmonic generation in fully depleted SOI (FDSOI) RF switches and methods of manufacture. The structure includes one or more active devices on a semiconductor on insulator material which is on top of a substrate; and a virtual drain region composed of a well region within the substrate and spaced apart from an active region of the one or more devices, the virtual drain region configured to be biased to collect electrons which would accumulate in the substrate.

Virtual drain for decreased harmonic generation in fully depleted SOI (FDSOI) RF switches

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Essex Junction, VT, United States of America

Edward J Nowak