Digital Equipment Corporation

Advanced Micro Devices Corporation

Marvell Asia Pte., Ltd.

Compaq Computer Corporation, Inc.

Freescale Semiconductor,inc.

Compaq Information Technologies Group, L.p.

Marvellworld Trade Ltd.

Edward J McLellan

Joel S Emer

Daniel Lawrence Leibholz

Gilbert M Wolrich

Jeffrey Adgate Dean

Carl Alan Waldspurger

William Edward Weihl

Srilatha Manne

James E Hicks, Jr

Bruce Alan Gieseke

George Z Chrysos

Robert A Yodlowski

Simon C Steely, Jr

Shubhendu Sekhar Mukherjee

David J Husak

David Kravitz

James Arthur Farrell

Elliot H Mednick

Mark A Sankey

Shay Gal-On

Donald A Priore

Andrew T Brown

Paul Schmitt

Thomas B Brightman

Andrew D Funk

Alexander Rucker

John F Brown

Samuel D Naffziger

Richard Eugene Kessler

Stephen Victor Kosonocky

John Kalamatianos

David Albert Carlson

Greg Sadowski

James Michael O'Connor

Derrick R Meyer

Rabin Sugumar

Michael T Clark

Rahul Razdan

Bruce Edwards

Paul S Keltcher

Kelvin Domnic Goveas

David Edward Kroesche

Michael L Golden

Daniel W Dobberpuhl

Richard E Klass

Steven Beigelmacher

Simon Steely

Rohit P Thakar

Seng Oon Toh

Scott McFarling

John A Kowaleski, Jr

Roy W Badeau

A heterogeneous processor system includes a first processor implementing an instruction set architecture (ISA) including a set of ISA features and configured to support a first subset of the set of ISA features. The heterogeneous processor system also includes a second processor implementing the ISA including the set of ISA features and configured to support a second subset of the set of ISA features, wherein the first subset and the second subset of the set of ISA features are different from each other. When the first subset includes an entirety of the set of ISA features, the lower-feature second processor is configured to execute an instruction thread by consuming less power and with lower performance than the first processor.

Instruction subset implementation for low power operation

The size of a cache is modestly increased so that a short pointer to a predicted next memory address in the same cache is added to each cache line in the cache. In response to a cache hit, the predicted next memory address identified by the short pointer in the cache line of the hit along with an associated entry are pushed to a next faster cache when a valid short pointer to the predicted next memory address is present in the cache line of the hit.

Method of cache prefetching that increases the hit rate of a next faster cache

An example embodiment combines use of a branch predictor with cache-like storage of previously executed branch targets to improve processor performance while minimizing hardware cost. The branch predictor is configured to predict both conditional branch and indirect branch targets and includes a combined predictor table configured to store at least one tagged conditional branch prediction in combination with at least one tagged indirect branch target prediction. The at least one tagged indirect branch target prediction is configured to include a predicted partial target address of a complete target address, the complete target address associated with an indirect branch instruction of a processor. The predictor includes prediction logic configured to use the predicted partial target address to produce a predicted complete target address of the complete target address for use by the processor prior to execution of the indirect branch instruction.

Combined conditional branch and indirect branch target predictor

Instructions are executed in a pipeline. Storage accessible to the pipeline stores branch prediction information characterizing results of branch instructions previously executed. A predicted branch result is provided, for at least some branch instructions, based on a selected predictor of multiple predictors. An actual branch result is provided based on an executed branch instruction, and the branch prediction information is updated based on the actual branch result. The predictors include: a first predictor that determines the predicted branch result based on at least a portion of the branch prediction information; and a second predictor that determines the predicted branch result independently from the branch prediction information.

Managing predictor selection for branch prediction

Instructions are executed in a pipeline of a processor, where each instruction is associated with a particular context. A first storage stores branch prediction information characterizing results of branch instructions previously executed. The first storage is dynamically partitioned into partitions of one or more entries. Dynamically partitioning includes updating a partition to include an additional entry by associating the additional entry with a particular subset of one or more contexts. A predicted branch result is determined based on at least a portion of the branch prediction information. An actual branch result provided based on an executed branch instruction is used to update the branch prediction information. Providing a predicted branch result for a first branch instruction includes retrieving a first entry from a first partition based at least in part on an identified first subset of one or more contexts associated with the first branch instruction.

Managing branch prediction information for different contexts

Methods and apparatus of delegating instructions or data from a CU to an NOC node in a network on chip (NOC) is disclosed. The NOC node executes the delegated instructions or processes the delegated data. An NOC controller (NCC), which is operatively coupled to the CU and the NOC node, facilitates delegating the instructions or data from the CU to the NOC node.

Methods and apparatus for processing in a network on chip (NOC)

A processor employs a set of replica paths at a processor to determine an operating frequency and voltage for the processor. The replica paths each represent one or more circuit paths at a functional module of the processor. The delays at the replica paths are normalized to increase the likelihood that the replica paths accurately represent the behavior of the circuit paths of the functional module. After normalization, a distribution of delay values is generated by varying, at each replica path, the delay at an output node of the replica path until a mismatch is detected between a signal at the output node of the replica path and the delayed representation of the signal. The resulting distribution of delay values can then be adjusted based on variations in reference voltages at the replica paths to account for potential distribution errors resulting from the reference voltage variations.

Replica path timing adjustment and normalization for adaptive voltage and frequency scaling

A method of implementing a mask load or mask store instruction by a processor is provided. The method may include receiving the mask load or mask store instruction, a location of a memory operand and a location of corresponding mask bits associated with the memory operand, breaking the received memory operand into a plurality of sub-operands and executing the mask load or mask store instruction on each of the plurality of sub-operands using a fastpath operation or using microcode, wherein the respective mask load or mask store instruction loads or stores each of the plurality of sub-operands based upon the corresponding mask bits.

Processor and method implemented by a processor to implement mask load and store instructions

In response to a processor core exiting a low-power state, a cache is set to a minimum size so that fewer than all of the cache's entries are available to store data, thus reducing the cache's power consumption. Over time, the size of the cache can be increased to account for heightened processor activity, thus ensuring that processing efficiency is not significantly impacted by a reduced cache size. In some embodiments, the cache size is increased based on a measured processor performance metric, such as an eviction rate of the cache. In some embodiments, the cache size is increased at regular intervals until a maximum size is reached.

Management of cache size

An integrated circuit () for use in processing streams of data generally and streams of packets in particular. The integrated circuit () includes a number of packet processors (), a table look up engine (), a queue management engine () and a buffer management engine (). The packet processors () include a receive processor (), a transmit processor () and a risc core processor (), all of which are programmable. The receive processor () and the core processor () cooperate to receive and route packets being received and the core processor () and the transmit processor () cooperate to transmit packets. Routing is done by using information from the table look up engine () to determine a queue () in the queue management engine () which is to receive a descriptor () describing the received packet's payload.

High speed and high throughput digital communications processor with efficient cooperation between programmable processing components

Digital communications processor

A technique for handling a conditional move instruction in an out-of-order data processor. The technique involves detecting a conditional move instruction within an instruction stream, and generating multiple instructions according to the detected conditional move instruction. The technique further involves replacing the conditional move instruction within the instruction stream with the generated multiple instructions. The generated multiple instructions are generated such that each of the generated multiple instructions executes using no more than two input ports of an execution unit. The generated multiple instructions include a first generated instruction that produces a condition result indicating whether a condition exists, and a second generated instruction that inputs the condition result as a portion of an operand which identifies a register of the out-of-order data processor. The second generated instruction performs a first move operation when the condition is determined to exist, and a second move operation when the condition is determined not to exist.

Implementation of a conditional move instruction in an out-of-order processor

A technique controls memory access requests. The technique involves acquiring a first series of requests including a prefetch request for performing a prefetch operation that prefetches a first set of instructions from a memory, and adding a first entry in a request queue in response to the prefetch request. The first entry identifies the prefetch operation. The technique further involves attempting to retrieve a second set of instructions from a cache to create a cache miss, and generating, in response to the cache miss, a second series of requests including a fetch request for performing a fetch operation that fetches the second set of instructions from the memory to satisfy the cache miss. The technique further involves acquiring the second series of requests that includes the fetch request, and adding a second entry in the request queue in response to the fetch request. The second entry identifies the fetch operation. The technique further involves invalidating the first entry in the request queue when the fetch request is acquired before the prefetch operation initiates, and maintaining the first entry in valid form in the request queue and performing the prefetch operation to completion when the fetch request is acquired after the prefetch operation initiates.

Methods and apparatus for minimizing the impact of excessive instruction retrieval

Growing community of inventors

Holliston, MA, United States of America

Edward J McLellan