Motorola Corporation

Freescale Semiconductor,inc.

Edward J Hathaway

Juxiang Ren

Michael C Wood

Lloyd P Matthews

David Shao Ling

Stephen Pickering

Connie Astrachan

Christian Vetterli

Robert E Garner

Thomas Lovell Portlock

Jayme W Richard

A memory management unit comprises register and control logic and arranged to support a microprocessor controller unit accessing physical address space via an address bus wherein the microprocessor controller unit comprises a program counter having a first address size, the memory management unit wherein the register and control logic comprises a register having a second address size greater than the first address size and arranged to provide an extended address bus between the microprocessor controller unit and physical address space.

Memory management unit and method of accessing an address

A circuit comprises a reference voltage generating circuit, a first switch, a second switch, and a capacitive element. The reference voltage generating circuit has an input and output terminal for providing a reference voltage. The first switch has a first terminal coupled to a first power supply voltage terminal, a second terminal coupled to the input terminal of the reference voltage generating circuit, and a control terminal for receiving a first control signal. The second switch has a first terminal coupled to the output terminal of the reference voltage generating circuit, a second terminal, and a control terminal for receiving a second control signal. The capacitive element has a first plate electrode coupled to the second terminal of the second switch, and a second plate electrode coupled to a second power supply voltage terminal.

Analog to digital converter with low power control

A Voltage Range Detection Circuit (VRDC) (8) determines the supply voltage range of the integrated circuit. In general, voltage detector (10) determines the voltage level of supply voltage V.sub.DD and stores the result of this determination in storage (12). Resistor network (14), which receives the stored result, configures itself in the proper resistor configuration for the determined supplied voltage such that a compare signal is generated that represents a Variable Low Voltage Detection (VLVD) switch point. Resistor network (14) outputs this generated VLVD switch point signal to a first input of comparator (18) to be compared with the constant level reference voltage output by voltage reference (16) at a second input of comparator (18). When the output of resistor network (14) drops below the reference voltage provided by voltage reference (16), comparator (18) outputs a reset signal to disable the chip because a low voltage condition has occurred. As will be appreciated, this single circuit implementation eliminates the need to provide multiple low voltage detection circuits to sense each of the possible voltage operating ranges.

Data processing system having an auto-ranging low voltage detection

A method and apparatus for generating integrated circuit test patterns (218) to test a functionality of integrated circuits. Module test stimuli (202) for each module present in an integrated circuit (10) are generated and retained (102). The module test stimuli (202) are translated to module drive patterns (206). Module expected patterns (210) are determined based on the module drive patterns (206) or module test stimuli (202) using module models (208). Integrated circuit data (216) describing the structure and timing of the integrated circuit (10) is used to translate the module patterns (212) into integrated circuit test patterns (218). The integrated circuit test patterns (212) are validated (220), transformed to test vectors (226), and the test vectors (226) are applied to the external connections of the integrated circuit (10) to test a functionality of the integrated circuit (10). A data processing system (300) creates the integrated circuit test patterns (218). The steps of the present invention are incorporated into a computer readable medium and a method for manufacturing and testing an integrated circuit (10).

Apparatus and method for generating integrated circuit test patterns

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Austin, TX, United States of America

Edward J Hathaway