Sandia Corporation

National Technology & Engineering Solutions of Sandia, LLC

Other

The United States of America As Represented by the United States

Edward I Cole

Paiboon Tangyunyong

Jerry M Soden

Joshua Beutler

Lyndon G Pierson

Ryan Helinski

Guillermo M Loubriel

Tan Q Thai

Jeremy A Walraven

Michael R Bruce

Rosalinda M Ring

Richard Eugene Anderson

Kenneth A Peterson

Victoria Jean Bruce

Charles F Hawkins

Jeffrey Stevens

David J Stein

Mary A Miller

Ann N Campbell

Daniel L Barton

Mark W Jenkins

Alejandro A Pimentel

John Joseph Clement

Described herein are various technologies pertaining to identifying counterfeit integrated circuits (ICs) by way of allowing the origin of fabrication to be verified. An IC comprises a main circuit and a test circuit that is independent of the main circuit. The test circuit comprises at least one ring oscillator (RO) signal that, when energized, is configured to output a signal that is indicative of a semiconductor fabrication facility where the IC was manufactured.

Test circuits for integrated circuit counterfeit detection

A method involving the non-destructive testing of a sample electrical or electronic device is provided. The method includes measuring a power spectrum of the device and performing a Principal Component Analysis on the power spectrum, thereby to obtain a set of principal components of the power spectrum. The method further includes selecting a subset consisting of some of the principal components, and comparing the subset to stored reference data that include representations in terms of principal components of one or more reference populations of devices. Based at least partly on the comparison, the sample device is classified relative to the reference populations.

Defect screening method for electronic circuits and circuit components using power spectrum anaylysis

A visualization method for screening electronic devices is provided. In accordance with the disclosed method, a probe is applied to a grid of multiple points on the circuit, and an output produced by the circuit in response to the stimulus waveform is monitored for each of multiple grid points where the probe is applied. A power spectrum analysis (PSA) produces a power spectrum amplitude, in each of one or more frequency bins, on the monitored output for each of the multiple grid points. The PSA provides a respective pixel value for each of the multiple grid points. An image is displayed, in which image portions representing the multiple grid points are displayed with the respective pixel values.

Scanning method for screening of electronic devices

The various technologies presented herein relate to utilizing visible light in conjunction with a thinned structure to enable characterization of operation of one or more features included in an integrated circuit (IC). Short wavelength illumination (e.g., visible light) is applied to thinned samples (e.g., ultra-thinned samples) to achieve a spatial resolution for laser voltage probing (LVP) analysis to be performed on smaller technology node silicon-on-insulator (SOI) and bulk devices. Thinning of a semiconductor material included in the IC (e.g., backside material) can be controlled such that the thinned semiconductor material has sufficient thickness to enable operation of one or more features comprising the IC during LVP investigation.

Visible light laser voltage probing on thinned substrates

A device sample is screened for defects using its power spectrum in response to a dynamic stimulus. The device sample receives a time-varying electrical signal. The power spectrum of the device sample is measured at one of the pins of the device sample. A defect in the device sample can be identified based on results of comparing the power spectrum with one or more power spectra of the device that have a known defect status.

Power spectrum analysis for defect screening in integrated circuit devices

A passive voltage contrast (PVC) system and method are disclosed for analyzing ICs to locate defects and failure mechanisms. During analysis a device side of a semiconductor die containing the IC is maintained in an electrically-floating condition without any ground electrical connection while a charged particle beam is scanned over the device side. Secondary particle emission from the device side of the IC is detected to form an image of device features, including electrical vias connected to transistor gates or to other structures in the IC. A difference in image contrast allows the defects or failure mechanisms be pinpointed. Varying the scan rate can, in some instances, produce an image reversal to facilitate precisely locating the defects or failure mechanisms in the IC. The system and method are useful for failure analysis of ICs formed on substrates (e.g. bulk semiconductor substrates and SOI substrates) and other types of structures.

System and method for floating-substrate passive voltage contrast

An apparatus and method are presented for identifying and mapping functional failures in an integrated circuit (IC) due to timing errors therein based on the generation of functional failures in the IC. This is done by providing a set of input test vectors to the IC and adjusting one or more: of the IC voltage, temperature or clock frequency; the rate at which the test vectors are provided to the IC; or the power level of a focused laser beam used to probe the IC and produce localized heating which changes the incidence of the functional failures in the IC which can be sensed for locating the IC circuit elements responsible for the functional failures. The present invention has applications for optimizing the design and fabrication of ICs, for failure analysis, and for qualification or validation testing of ICs.

Apparatus and method for analyzing functional failures in integrated circuits

A thermally-induced voltage alteration (TIVA) apparatus and method are disclosed for analyzing a microelectromechanical (MEM) device with or without on-board integrated circuitry. One embodiment of the TIVA apparatus uses constant-current biasing of the MEM device while scanning a focused laser beam over electrically-active members therein to produce localized heating which alters the power demand of the MEM device and thereby changes the voltage of the constant-current source. This changing voltage of the constant-current source can be measured and used in combination with the position of the focused and scanned laser beam to generate an image of any short-circuit defects in the MEM device (e.g. due to stiction or fabrication defects). In another embodiment of the TIVA apparatus, an image can be generated directly from a thermoelectric potential produced by localized laser heating at the location of any short-circuit defects in the MEM device, without any need for supplying power to the MEM device. The TIVA apparatus can be formed, in part, from a scanning optical microscope, and has applications for qualification testing or failure analysis of MEM devices.

Thermally-induced voltage alteration for analysis of microelectromechanical devices

A thermally-induced voltage alteration (TIVA) apparatus and method are disclosed for analyzing an integrated circuit (IC) either from a device side of the IC or through the IC substrate to locate any open-circuit or short-circuit defects therein. The TIVA apparatus uses constant-current biasing of the IC while scanning a focused laser beam over electrical conductors (i.e. a patterned metallization) in the IC to produce localized heating of the conductors. This localized heating produces a thermoelectric potential due to the Seebeck effect in any conductors with open-circuit defects and a resistance change in any conductors with short-circuit defects, both of which alter the power demand by the IC and thereby change the voltage of a source or power supply providing the constant-current biasing. By measuring the change in the supply voltage and the position of the focused and scanned laser beam over time, any open-circuit or short-circuit defects in the IC can be located and imaged. The TIVA apparatus can be formed in part from a scanning optical microscope, and has applications for qualification testing or failure analysis of ICs.

Thermally-induced voltage alteration for integrated circuit analysis

An apparatus and method for defect and failure-mechanism testing of integrated circuits (ICs) is disclosed. The apparatus provides an operating voltage, V.sub.DD, to an IC under test and measures a transient voltage component, V.sub.DDT, signal that is produced in response to switching transients that occur as test vectors are provided as inputs to the IC. The amplitude or time delay of the V.sub.DDT signal can be used to distinguish between defective and defect-free (i.e. known good) ICs. The V.sub.DDT signal is measured with a transient digitizer, a digital oscilloscope, or with an IC tester that is also used to input the test vectors to the IC. The present invention has applications for IC process development, for the testing of ICs during manufacture, and for qualifying ICs for reliability.

Apparatus and method for defect testing of integrated circuits

An electron beam apparatus and method for testing a circuit. The electron beam apparatus comprises an electron beam incident on an outer surface of an insulating layer overlying one or more electrical conductors of the circuit for generating a time varying or alternating current electrical potential on the surface; and a measurement unit connected to the circuit for measuring an electrical signal capacitively coupled to the electrical conductors to identify and map a conduction state of each of the electrical conductors, with or without an electrical bias signal being applied to the circuit. The electron beam apparatus can further include a secondary electron detector for forming a secondary electron image for registration with a map of the conduction state of the electrical conductors. The apparatus and method are useful for failure analysis or qualification testing to determine the presence of any open-circuits or short-circuits, and to verify the continuity or integrity of electrical conductors buried below an insulating layer thickness of 1-100 .mu.m or more without damaging or breaking down the insulating layer. The types of electrical circuits that can be tested include integrated circuits, multi-chip modules, printed circuit boards and flexible printed circuits.

Capacitive charge generation apparatus and method for testing circuits

A scanning electron microscope apparatus and method are described for detecting and imaging open-circuit defects in an integrated circuit (IC). The invention uses a low-energy high-current focused electron beam that is scanned over a device surface of the IC to generate a charge-induced voltage alteration (CIVA) signal at the location of any open-circuit defects. The low-energy CIVA signal may be used to generate an image of the IC showing the location of any open-circuit defects. A low electron beam energy is used to prevent electrical breakdown in any passivation layers in the IC and to minimize radiation damage to the IC. The invention has uses for IC failure analysis, for production-line inspection of ICs, and for qualification of ICs.

Integrated circuit failure analysis by low-energy charge-induced voltage

A magnetic force microscopy method and improved magnetic tip for detecting and quantifying internal magnetic fields resulting from current of integrated circuits. Detection of the current is used for failure analysis, design verification, and model validation. The interaction of the current on the integrated chip with a magnetic field can be detected using a cantilevered magnetic tip. Enhanced sensitivity for both ac and dc current and voltage detection is achieved with voltage by an ac coupling or a heterodyne technique. The techniques can be used to extract information from analog circuits.

Magnetic force microscopy method and apparatus to detect and image

An apparatus and method are described for analyzing an integrated circuit (IC), The invention uses a focused light beam that is scanned over a surface of the IC to generate a light-induced voltage alteration (LIVA) signal for analysis of the IC, The LIVA signal may be used to generate an image of the IC showing the location of any defects in the IC; and it may be further used to image and control the logic states of the IC. The invention has uses for IC failure analysis, for the development of ICs, for production-line inspection of ICs, and for qualification of ICs.

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Albuquerque, NM, United States of America

Edward I Cole