Samsung Electronics Co., Ltd.

Edward H Yu

Roney S Wong

Le Trong Nguyen

Heonchul Park

Ho Dai Truong

Ted Nguyen

Sanghyeon Baeg

Kathy Ying Chen

A vector processor provides a data path divided into smaller slices of data, with each slice processed in parallel with the other slices. Furthermore, an execution unit provides smaller arithmetic and functional units chained together to execute more complex microprocessor instructions requiring multiple cycles by sharing single-cycle operations, thereby reducing both costs and size of the microprocessor. One embodiment handles 288-bit data widths using 36-bit data path slices. Another embodiment executes integer multiply and multiply-and-accumulate and floating point add/subtract and multiply operations using single-cycle arithmetic logic units. Other embodiments support 8-bit, 9-bit, 16-bit, and 32-bit integer data types and 32-bit floating data types.

Execution unit for processing a data stream independently and in parallel

An apparatus for multiplexing a pair of test clock signals and a pair of system clock signals onto a pair of output clock signals includes a first means for coupling a first test clock signal to a first output clock signal when a test mode control signal is active, for driving the first output clock signal to an inactive clock signal level when the test mode control signal transitions to an inactive state, and for coupling a first system clock signal to the first output clock signal beginning with a first full clock pulse of the first system clock signal which occurs after the test mode control signal transitions to the inactive state. The apparatus further includes a second means for coupling a second test clock signal to a second output clock when the test mode control signal is active, for driving the second output clock to the inactive clock signal level when the test mode control signal transitions to the inactive state, and for coupling a second system clock signal to the second output clock beginning with a first full clock pulse of the second system clock signal which occurs after the first full clock pulse of the first system clock signal. When exiting the test mode the apparatus ensures that both first and second output clock signals are brought (or held) to an inactive clock signal level, and that system operation begins with the first system clock signal.

Synchronous multiplexer for clock signals

A modular two level nine bit shift apparatus has a second level shifter which receives nine input data bits and second level shift signals. The second level shifter shifts the nine data bits by 0, 3 or 6 bit positions according to the second level shift signals and outputs nine second level data bits. A first level shifter receives the nine second level data bits and first level shift signals. The first level shifter shifts the nine second level data bits by 0, 1 or 2, bit positions according to the first level shift signals. The first and second level shifter combine to provide a shift of from 0 to 8 bits. The nine bit shifter can also accommodate eight bit data. The 9 bit shift count is decoded by dividing the count into a first block (0, 1, 2), a second block (3, 4, 5) and a third block (6, 7, 8). Block select signals select one of the first, second and third blocks and the bit select signals select one of the three shift counts within each block. A decode of the block select signals are coupled to the second level shifter as the second level shift signal and a decode of the bit select signals are coupled to the first level shifter as the first level shift signal. Therefore, the block select signals specify shifts of 0, 3, or 6 bits and the bit select signals specify shifts of 0, 1 or 2 bits, to specify a total shift of between 0 and 8 bits. The nine bit two level modular shifter can be used to create a wider shift comprised of three levels. The third level shifter which includes 4 9-bit 4:1 multiplexers, receives thirty six input bits and third level shift signals. The third level shifter outputs the thirty six input bits shifted by 0, 9, 18, or 27, which are then supplied to four two level 9 bit shifters to provide a full 36 bit shift/rotate operation.

Ternary based shifter that supports multiple data types for shift

In an integrated circuit, a clock to simulate the circuit's normal operation is generated from the JTAG clock input TCK.

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Newark, CA, United States of America

Edward H Yu