Honeywell G.m.b.h.

Edward H Forrester

Robert H Douglas

Steven A Rose

Harry Keller

David Murray

In a data protection apparatus for a multiple CPU system having a common or multiported bulk memory, an interface structure is associated with each of the CPU's. The interface structure cooperates with a firmware engine which is, in turn, a part of the interface control means which controls the transfer of data between the common bulk memory apparatus and each of the several CPU's in the system. Signals generated by the individual CPU's indicative of an emergency situation are applied as input signals to the interface structure. The interface structure then translates those signals into an attention flag signal and signals identifying the source or nature of the emergency. The firmware engine then responds to those signals and effects the necessary measures to protect the data relative to the affected CPU.

Protection apparatus for multiple processor systems

There has been provided, in a computer system, a control unit having authority over a plurality of subordinate units with differing response times. The control unit addresses and issues command instructions to selected ones of the subordinate units then waits for an acknowledgement of completion from the addressed units before going to the next step in its routine. To prevent the control unit from being hung-up in the event of a failure of response from the subordinate unit, time-out means are provided for releasing the control unit for further operation. Since the response times of the individual subordinate units are unknown to the control unit, a unique time-out circuit is provided for each of the subordinate units, each time-out circuit being commensurate with the response time of the associated subordinate unit.

Time-out interface means

In a computer system wherein a number of peripheral devices contend with each other for access to a communication bus, a priority selection system is provided. The priority selection system includes priority address code setting means as a part of each of the peripheral devices. A contention bus is provided to which all of the peripheral devices are connected in parallel. Logic means are provided as a functional part of each of the peripheral devices. A logic means are responsive to the setting of the priority address codes to resolve the priority selection among the several contenders. With the logic means and the address code means being a part of the peripheral devices, the selection is independent of card cage slot position or of slot gaps. The system is also independent of the length of the communication bus.

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Edward H Forrester