Amdahl Corporation

Other

Edward G Ryba

David Weiss

Allan J Zmyslowski

Peter H Lipman

Jefferson J Connell

Theodore C Bernard

Gary A Browning

An access control apparatus in a computer system for controlling access to an ALB. A host ALBID register and a guest ALBID register is provided for storing a host and a guest ALB identifier (ALBID) and a host and a guest ALBID validity indicator. Control State Software generates and stores the host and guest ALBIDs in the host and guest ALBID registers and marks valid the host and guest ALBID validity indicator whenever a host or guest mode is initiated or a logical purge is requested by a logical processor and for storing the host or guest ALBID stored in the host and guest ALBID registers when an ALB entry is made in the ALB by a logical processor. Access to an ALB entry by a logical processor is permitted when the logical processor is in the host mode if the ALBID in the ALB entry matches the host ALBID stored and the valid indicator is marked valid in the host ALBID register and when the logical processor is in the guest mode if the ALBID in the ALB entry matches the guest ALBID stored and the valid indicator is marked valid in the guest ALBID register. A host logical purge is accomplished by marking invalid the host and guest validity indicators in the host and guest ALBID registers. A guest Logical purge is accomplished by marking invalid the guest validity indicator in the guest ALBID register.

Access control mechanism controlling access to and logical purging of

A random access memory (RAM) complex that can concurrently read and write to different addresses. The memory complex includes two RAMs, each having an address selector, includes a data out multiplexer for selecting outputs from one of the RAM's. A tag array stores an array of tag, one for each address in the RAM's. The tag marks which one of the two RAM's has the valid data for the corresponding read address. During a concurrent read and write cycle, the tag selects the read address for one RAM, selects the write address for the other RAM and a staged copy of the tag controls the multiplexer to select data from the correct RAM for the data out.

Memory having concurrent read and writing from different addresses

A pipeline interlock mechanism which insures the logical integrity of architected control quantities when used to access Domain Storage from Control State. A hardware Domain Interlock (DOMI) is provided to detect the start of execution in Control State of any instruction which modifies architected controls governing the access of Domain storage, and which insures that any subsequent potential access to Domain storage remains interlocked in the D-cycle until the modified controls become valid.

Domain interlock

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Milpitas, CA, United States of America

Edward G Ryba