Hewlett-packard Company

Agilent Technologies, Inc.

Abbott Laboratories Corporation

Edward G Pumphrey

Richard A Nygaard, Jr

Frederic L Clark

Benton A Durley, Iii

Keith C Griggs

Christopher Koerner

Charles L Davis

Alberto Gutierrez, Jr

Lawrence Spritzer

John G Pumphery

Paul E Garrett

A system and method are provided for detecting a stable region in a data signal to facilitate the alignment between a data signal and a corresponding clock signal. The system includes a processor coupled to a local interface and a memory coupled to the local interface. The system also includes a boundary detection circuit configured to perform a simultaneous sampling of a reference signal and a delayed reference signal to ascertain a degree of stability of a position in the reference signal. The reference signal is the signal received from the target system and the delayed reference signal is a delayed copy of the reference signal. The system also includes boundary detection logic stored on the memory and executed by the processor to control the operation of the boundary detection circuit. The boundary detection logic includes logic to detect a boundary of the stable region of the reference.

System and method for adjusting a sampling time in a logic analyzer

A delay element for fine tuning the position in time of timing edges of an input signal, comprising a first and a second inventer, each comprising a data input, a control input and a data output. The delay element further comprises a node comprised of a connection between the data output of the first inverter and the data input of the second inverter. An adjustable control voltage is included for applying a biasing voltage to the first and second control inputs to thereby control the amount of charge supplied to the node. Finally, the variable capacitance means is connected to the node for applying finite amounts of capacitance to the node to delay and thereby fine tune in time the timing edges of the input signal propagating from the first inverter to the second inverter.

Programmable capacitance delay element having inverters controlled by

Apparatus for measuring electrolyute concentrations in fluid samples. The apparatus includes an ion selective electrode having a plurality of ion selective detection sites. Each site has an affinity for a preselected electrolyte of interest and generates a potential having a magnitude related to the concentration of the corresponding electrolyte in the sample. A voltage to optical transducer circuit is provided to convert the voltage differentials to optical signals having intensity related to the concentration of the electrolytes in a first embodiment, a digital code related to the concentration of the electrolytes in a second embodiment, and an optical absorption or density value related to the concentration of the electrolytes in a third embodiment. The optical signals are suitable for detection by conventional optical detector apparatus of assay instruments and may be processed using conventional two point linear interpolation techniques to determine the concentrations of the preselected electrolytes.

Apparatus for measuring electrolytes utilizing optical signals related

An NMOS analog voltage comparator is disclosed having two matching cascaded inverter-pairs. The comparator has fast response time, is not sensitive to temperature variations while operating, and operates independent of integrated circuit parameter variations encountered during circuit manufacture.

NMOS analog voltage comparator

Growing community of inventors

Colorado Springs, CO, United States of America

Edward G Pumphrey