Skyworks Solutions, Inc.

Edward F Lawrence

David Steven Ripley

Joshua Kawika Ellis

Yuan Li

Philip Howard Thompson

Norbert Andrew Schmitz

Darryl Earl Evans

Michael Glasbrener

Mark N Ayvazian

David M Johnson

Leanne O Flack

Darryl E Evans

Aspects of this disclosure relate tuning an impedance presented to a common port of a multi-throw switch and a tunable notch filter coupled to the common port. The impedance presented to the common port can be tuned based on an impedance associated with a throw of the multi-throw switch that is activated. According to embodiments of this disclosure, a shunt inductor in parallel with a tunable capacitance circuit can tune the impedance presented to the common port of the multi-throw switch. In certain embodiments, the tunable notch filter includes a series LC circuit in parallel with a tunable impedance circuit.

Contour tuning circuit and related systems and methods

Described herein are circuits and methods for improving switch performance when overdriving the gate by adding a delay on a PMOS gate voltage such that it can turn on the PMOS during switch state transition to allow charge/discharge of the switch body voltage faster and it can turn off once the process is complete. For example, back-to-back diodes can be used to separate the PMOS gate and drain. This can reduce leakage current and can reduce or eliminate the potential for breakdown of the switch.

Circuits and methods for biasing switch body

Aspects of this disclosure relate tuning an impedance presented to a common port of a multi-throw switch. The impedance can be tuned based on an impedance associated with a throw of the multi-throw switch that is activated. This can, for example, provide impedance matching for a duplexer port coupled to a throw of the multi-throw switch that is activated. According to embodiments of this disclosure, a shunt inductor in parallel with a tunable capacitance circuit can tune the impedance presented to the common port of the multi-throw switch. The shunt inductor and the tunable capacitance circuit can be coupled to a node in a signal path between an antenna switch and an antenna port in some embodiments.

Contour tuning circuit

Aspects of this disclosure relate to a tunable notch filter. In an embodiment, a tunable notch filter includes a series LC circuit in parallel with a tunable impedance circuit, and the tunable notch filter is in a radio frequency signal path associated with a common port of a multi-throw radio frequency switch. According to certain embodiments, the tunable notch filter can be in a radio frequency signal path between an antenna switch and an antenna port.

Tunable notch filter

Tunable notch filter and contour tuning circuit

An exemplary antenna switching circuit comprises first, second, third and fourth switches. The first switch is activated by a first control signal for establishing a connection between a first transmit port and an antenna; the second switch is activated by a second control signal for establishing a connection between a second transmit port and the antenna; the third switch is activated by a third control signal for establishing a connection between a first receive port and the antenna; and the fourth switch is activated by the third control signal for establishing a connection between a second receive port and the antenna. With this arrangement, the first receive port and the second receive port are simultaneously connected to the antenna when the third switch and the fourth switch are activated by the third control signal.

Efficient multiple-band antenna switching circuit

A non-linear transistor circuit uses separate signal biasing and DC biasing to improve the power efficiency while preventing thermal runaway. An improved amplifier using this circuit has a DC bias voltage supply. Using separate biasing of the DC supply voltage and the signal allows a large value resistance for the DC bias network to prevent thermal runaway and a small value resistance for the signal biasing network to improve the circuit's efficiency. A point of thermal equilibrium is reached when the voltage drop across the DC bias resistance sufficiently reduces the voltage between the transistor's base and emitter, V , the base current, the collector current, and the junction temperature, resulting in thermal equilibrium.

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Marion, IA, United States of America

Edward F Lawrence