International Business Machines Corporation

Edward E Horton, Iii

Leendert M Huisman

Glen E Richard

Leah M Pastel

Thomas Webster Bartenstein

Raymond J Rosner

Douglas C Heaberlin

L Owen Farnsworth

Francis Woytowich

Brian Robert Kessler

A method of testing a semiconductor device having a memory is disclosed. The method includes selecting a portion of the memory; testing the selected portion of the memory; designating the selected portion of the memory as a designated memory in response to an acceptable testing result; and storing data in the designated portion of the memory for retrieval at a later time. Provision for soft repair of the selected memory is made. Test data can be compressed before being stored in the designated memory.

Internal cache for on chip test data storage

A process for diagnosing test result data produced during boundary scan testing of a circuit device having a plurality of boundary scan latches at endpoints interconnected in a plurality of nets. The process identifies the particular endpoint that is defective out of all the endpoints in a defective net so that a repair can be efficiently directed to the identified endpoint. The process looks for recognizable patterns of failures in failure data resulting from each test pattern in a boundary scan test, particularly the symptom pattern of a failed endpoint that fails to drive all other endpoints on the net when acting as a driver and fails to receive data from all other endpoints when acting as a receiver.

Process for identifying defective interconnection net end points in

A complete fail signature for an integrated circuit is compared to at least one predicted fail signature generated using a hardware fault simulator to generate fault candidates for the integrated circuit representing the most likely faults present within the tested circuit or device. The complete fail signature may be generated by obtaining physical test data for the integrated circuit derived by testing the integrated circuit using test vectors and comparing the results of the testing with the test results of a flawless integrated circuit to generate a fail signature. Also, the complete fail signature may be generated by compiling the logic of the integrated circuit into binary language suitable for simulation in a hardware fault simulator and compiling the test vectors into binary language suitable for simulation in the hardware fault simulator. The logic function of the integrated circuit may be simulated on the hardware fault simulator and the test vectors applied to the hardware fault simulator to determine an expected output of the integrated circuit. The expected output may be combined with the fail signature to generate a complete fail signature representative of a complete output pattern of the integrated circuit.

Method and system of fault diagnosis of application specific electronic

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Westford, VT, United States of America

Edward E Horton, Iii