Advanced Micro Devices Corporation

Edward E Ehrichs

Chris L Wooten

Mark Brandon Fuselier

Paul Raymond Besser

Karsten Wieczorek

James F Buller

Martin Trentzsch

David E Brown

Travis R Lewis

S Doug Ray

Laura Pressley

James C Pattison

Chad Weintraub

Scott Goad

Travis D Kirsch

Hang Thi Yen Black

By providing a gate dielectric material of increased thickness for P-channel transistors compared to N-channel transistors, degradation mechanisms, such as negative bias threshold voltage instability, hot carrier injection and the like, may be reduced. Due to the enhanced reliability of the P-channel transistors, overall production yield for a specified quality category may be increased, due to the possibility of selecting narrower guard bands for the semiconductor device under consideration.

Gate dielectrics of different thickness in PMOS and NMOS transistors

The present invention is directed to controlling wafer temperature during rapid thermal processing. Regions and devices in an integrated circuit may be surrounded, inlayed, and overlaid with high absorptive structures to increase the average absorptivity of a region. This technique is useful for increasing average absorptivity in dense capacitive regions of integrated circuits. These dense capacitive regions typically have large areas of exposed low absorptivity polysilicon during rapid thermal processing steps. The exposed low absorptivity regions absorb less energy than other regions of the integrated circuit. As such, the RTP temperature varies between regions of the integrated circuit, causing variance in device size and characteristics. Adding absorptivity structures increase the absorption of energy in these regions, reducing temperature variance during RTP. The reduced temperature variance results in uniform manufacture of device.

High emissivity capacitor structure

Various methods of fabricating halo regions are disclosed. In one aspect, a method of manufacturing is provided that includes forming a symmetric transistor gate and an asymmetric transistor gate on a substrate. The symmetric and asymmetric transistor gates are substantially perpendicular. A mask is formed on the substrate with a first opening and a second opening. The first opening is sized to enable implantation of first and second halo regions beneath the symmetric transistor gate. The second opening is sized to enable implantation of a third halo region beneath and on one but not both sides of the asymmetric gate. The first and second halo regions are formed beneath the first gate by implanting through the first opening toward opposite sides of the symmetric gate. The third halo region is formed beneath and proximate one but not both sides of the asymmetric transistor gate by implanting through the second opening.

Simplified masking for asymmetric halo

A method and system to locate and detect voids in films that are involved in critical dimension (CD) structures and non-critical dimension structures in semiconductor devices are presented. One or more test structures (resolution devices) are formed on a semiconductor wafer. A scanning electron microscope is operated in voltage contrast mode to obtain a digital representation of the test structure. The voltage contrast image of the test structure is then analyzed with a system which automates the location, identification, and categorization of voids in the test structure. Additionally, the method is more sensitive to electrical marginalities caused by voids than other wafer electrical testing methods. The method is suitable inline monitoring during a manufacturing process by utilizing the automation of void identification, location, and categorization as a process monitoring parameter.

Method, system and apparatus to detect defects in semiconductor devices

Various methods of fabricating halo regions are disclosed. In one aspect, a method of manufacturing is provided that includes forming a symmetric transistor and an asymmetric transistor on a substrate. A first mask is formed on the substrate with a first opening to enable implantation formation of first and second halo regions proximate first and second source/drain regions of the symmetric transistor. First and second halo regions of a first dosage are formed beneath the first gate by implanting off-axis through the first opening. A second mask is formed on the substrate with a second opening to enable implantation formation of a third halo region proximate a source region of the second asymmetric transistor while preventing formation of a halo region proximate a drain region of the asymmetric transistor. A third halo region of a second dosage greater than the first dosage is formed by implanting off-axis through the second opening.

Asymmetric halo implants

A semiconductor component having an optical interconnect formed thereover and a method for manufacturing the semiconductor component. The semiconductor component has a transistor coupled to a light emitting device and another transistor coupled to a light detecting device by a metallization system. The light emitting device is optically coupled to the light detecting device by an optical interconnect formed over the transistors and the metallization system.

Semiconductor component and method of manufacture

A method for asymmetric spacer formation integratable into a manufacturing process for integrated circuit semiconductor devices is presented. The method comprises forming a gate structure over a substrate, and forming a sidewall layer overlying the gate structure and substrate, wherein the sidewall layer comprises a first portion overlying a first sidewall of the gate structure. A photoresist structure is formed adjacent to the first portion, and subjected to an ion beam. The photoresist structure serves to shield at least part of the first portion from the ion beam. During irradiation, the wafer is oriented such that a non-orthogonal tilt angle exists between a path of the ion beam and a surface of the first sidewall. Formation of asymmetric spacers is possible because radiation damage to unshielded sidewall portions permits subsequent etches to proceed at a faster rate.

Method for asymmetric spacer formation

In a method for mounting an integrated circuit onto a substrate in a flip-chip configuration, a circuit alignment feature on the processed surface of the integrated circuit and a substrate alignment feature on the mounting surface of the substrate are used to accurately align a set of bonding pads on the processed surface of the integrated circuit with a corresponding set of contact pads on the mounting surface of the substrate. The positions of the circuit and substrate alignment features are determined, and a separation between these alignment features which will result in accurate alignment of the bonding pads to the corresponding contact pads is calculated. The circuit is moved with respect to the substrate in order to achieve this predetermined separation. The method may be carried out using an apparatus which includes a die placement fixture and a substrate placement fixture. An alignment feature detection system is used to determine positions of circuit and substrate alignment features, and an alignment controller coupled to the alignment feature detection system is adapted to move the circuit fixture with respect to the substrate fixture such that predetermined separation between the circuit and substrate alignment features is achieved.

Method and apparatus for accurate alignment of integrated circuit in flip-chip configuration

A method, system, and storage medium for determining retide tilt in a lithographic system is provided. Test patterns contained on a reticle are printed in a photoresist located on an upper surface of a semiconductor substrate by a lithographic system. The test patterns may include three posts of different diameters wherein one of the diameters is approximately equal to the minimum allowable feature size printable by the lithographic system. Images of the test patterns are measured by a scanning electron microscope under the control of a computer system. The computer system then assesses the measured images of the test patterns to determine if the reticle tilt is acceptable or unacceptable. In one embodiment, the computer system may assess the measured images by comparing the measured images to predetermined images of the test patterns for different focus conditions. The computer system may also calculate the amount of reticle tilt. In an alternative embodiment, the computer system may assess the measured images by comparing the measured images to each other.

Method for automated determination of reticle tilt in a lithographic system

A semiconductor wafer review system and method. A method and system for front and back side review of semiconductor wafers is provided in various embodiments. Inspection data for the front side is used to position the wafer for front side review, and a wafer inverter is provided to flip the wafer for back side review. Inspection data for the back side is used to position the wafer for back side review.

Semiconductor wafer review system and method

The present invention is directed to a method for manufacturing semiconductor devices. The method generally comprises forming a plurality of process layers on a wafer,. The wafer has an edge region,with a number of defects,existing thereon. Thereafter, the method comprises removing all or a substantial portion of the defects,on the edge region,of the wafer

Wafer edge polish

A method is presented for devising a model to determine the damage potential of wafer defects. The model takes into account both the defects' type and size. Wafer defects are the most major cause of depressed yields in semiconductor manufacturing. The wafers are first scanned to detect and identify the defects. There are several available tools that can detect and/or categorize the defects by type and size. A model is then formed to predict the probability (single probability) that a single defect on a die will not cause it to be nonfunctional. This model must depend on the size of the defect and an additional undetermined parameter which is specific to the type of the defect. Assuming that the effect of different defects is independent, the probability that a die will be functional when having multiple defects is then simply given by the product of all the single probabilities. At the end of the manufacturing process, the wafers can be electrically tested to determine whether the die are functional or not. An error function can then be formed by adding together the square of: for functional die, one minus the predicted probability; for nonfunctional die, the predicted probability minus zero. A good model should predict close to one for functional die and close to zero for nonfunctional die. By numerically minimizing this error function, the undetermined parameters can be computed. These parameters can then be used to predict the damage potential of defects for future wafers.

Method for determining the damage potential of the different types of wafer defects

A semiconductor wafer analysis system and method. In various embodiments, methods and systems are described for inspection and review of semiconductor wafers. Wafer inverters are provided, and inspection data is gathered for both the front and back sides of the wafers. The wafer inverters are also available at wafer review stations so that both the front and back sides of the wafers can be reviewed with a microscope.

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Austin, TX, United States of America

Edward E Ehrichs