International Business Machines Corporation

Globalfoundries Inc.

Ultratech, Inc.

Edward Crandal Cooney, Iii

Anthony K Stamper

Jeffrey P Gambino

Thomas L McDevitt

Andrew Herbert Simon

John Anthony Fitzsimmons

Vincent James McGahay

Michael Wayne Lane

Lee Matthew Nicholson

Daniel C Edelstein

Zhong-Xiang He

Matthew Earl Colburn

Thomas M Shaw

William Joseph Murphy

Robert Michael Geffken

Timothy Joseph Dalton

William Thomas Motsiff

Sampath Purushothaman

Elbert Emin Huang

Satyanarayana Venkata Nitta

Cornelia K Tsang

Felix Patrick Anderson

Sujatha Sankaran

Edmund Juris Sprogis

Robert K Leidy

Hyun K Lee

Charles S Musante

Gary L Milo

Patrick S Spinney

Arne Watson Ballantine

Paul Stephen Andry

Xiao Hu Liu

Tom C Lee

Fen Chen

Peter James Lindgren

Ronald A Warren

Jeffrey D Gilbert

David Craig Strippe

Jason P Ritter

Jonathan M Pratt

Anna Tilley

Steven P Barkyoumb

James Stuart Dunn

Stephen Ellinwood Luce

Leathen Shi

Christy Sensenich Tyberg

Jonathan Daniel Chapple-Sokol

Dale Warner Martin

David C Thomas

Keith Edward Downes

John G Twombly

Mark P Murray

Michael S Dusablon

David C Mosher

Amanda L Piper

Dorreen Jane Ossenkop

Thomas W Weeks

Elizabeth T Webster

Amy L Myrick

Robert G Miller

Cyprian Emeka Uzoh

Stephen Mark Rossnagel

Stephen Edward Greco

Richard Stephen Graf

Darryl D Restaino

Nancy Anne Greco

BethAnn Rainey

Ronald Dean Goldblatt

Dinh Dang

Pavel Smetana

Brett T Cucci

Glenn Robert Miller

George A Dunbar, Iii

David A DeMuynck

Eva A Shah

Sarah A McTaggart

Mark D Dupuis

John C Hall

Thomas C Lee

Frank V Liucci

Josef W Korejwa

Steven S Williams

Laurie M Krywanczyk

Cheryl Faltermeier

Melissa J Roma

David H Yao

Jeffrey L Thompson

BethAnn Rainey Lawrence

Doreen Jane Ossenkop

Gregory S Chrisman

Brian P Conchieri

Bruce A Root

Various aspects include an integrated circuit (IC), design structure, and a method of making the same. In one embodiment, the IC includes: a substrate; a dielectric layer disposed on the substrate; a set of wire components disposed on the dielectric layer, the set of wire components including a first wire component disposed proximate a second wire component; a bond pad disposed on the first wire component, the bond pad including an exposed portion; a passivation layer disposed on the dielectric layer about a portion of the bond pad and the set of wire components, the passivation layer defining a wire structure via connected to the second wire component; and a wire structure disposed on the passivation layer proximate the bond pad and connected to the second wire component through the wire structure via.

Integrated circuit including wire structure, related method and design structure

Disclosed is a method of forming back end of the line (BEOL) metal levels with improved dielectric capping layer to metal wire adhesion. The method includes process step(s) designed to address dielectric capping layer to metal wire adhesion, when the metal wire(s) in a given metal level are relatively thick. These process step(s) can include, for example: (1) selective adjustment of the deposition tool used to deposit the dielectric capping layer onto metal wires based on the pattern density of the metal wires in order to ensure that those metal wires actually achieve a temperature between 360&#xb0; C.-400&#xb0; C.; and/or (2) deposition of a relatively thin dielectric layer on the dielectric capping layer prior to formation of the next metal level in order to reduce the tensile stress of the metal wire(s) below without causing delamination. Also disclosed is an IC chip formed using the above-described method.

Method for forming BEOL metal levels with multiple dielectric layers for improved dielectric to metal adhesion

A structure and a method. The structure includes a semiconductor substrate; a stack of wiring levels from a first wiring level to a last wiring level, the first wiring level closest to the semiconductor substrate and the last wiring level furthest from the semiconductor substrate, the stack of wiring levels including an intermediate wiring level between the first wiring level and the last wiring level; active devices contained in the semiconductor substrate and the first wiring level, each wiring level of the stack of wiring levels comprising a dielectric layer containing electrically conductive wire; a trench extending from the intermediate wiring level, through the first wiring level into the semiconductor substrate; and a chemical agent filling the trench, portions of at least one wiring level of the stack of wiring levels not chemically inert to the chemical agent or a reaction product of the chemical agent.

Semiconductor chip with anti-reverse engineering function

Aspects of the present disclosure include a test structure that includes two or more devices. Each device includes a wire disposed within a dielectric and a first via disposed over the wire and in electrical contact with the wire. Each device includes a test pad electrically connected to the first via and a polysilicon resistor electrically connected to the wire. Each of the polysilicon resistors of the two or more devices are electrically tied together. A method for forming the interconnect structure to be used for testing is also provided.

Test structure for monitoring interface delamination

An integrated circuit (IC), design structure, and a method of making the same. In one embodiment, the IC includes: a substrate; a dielectric layer disposed on the substrate; a set of wire components disposed on the dielectric layer, the set of wire components including a first wire component disposed proximate a second wire component; a bond pad disposed on the first wire component, the bond pad including an exposed portion; a passivation layer disposed on the dielectric layer about a portion of the bond pad and the set of wire components, the passivation layer defining a wire structure via connected to the second wire component; and a wire structure disposed on the passivation layer proximate the bond pad and connected to the second wire component through the wire structure via.

Structures that include an identification marking and fabrication methods for such structures. A chip is formed within a usable area of a wafer, and a marking region is formed on the wafer. The marking region is comprised of a conductor used to form a last metal layer of an interconnect structure for the chip. The identification marking is formed in the conductor of the marking region. After the identification marking is formed, a dielectric layer is deposited on the marking region. The dielectric layer on the marking region is planarized.

Laser scribe structures for a wafer

Structure for BEOL metal levels with multiple dielectric layers for improved dielectric to metal adhesion

A method including forming a first metal wire in a first dielectric layer, the first metal wire including a first vertical side opposite from a second vertical side; and forming a second metal wire in a second dielectric layer above the first dielectric layer, the second metal wire including a third vertical side opposite from a fourth vertical side, where the first vertical side is laterally offset from the third vertical side by a first predetermined distance, and the second vertical side is laterally offset from the fourth vertical side by a second predetermined distance, where the first metal wire and the second metal wire are in direct contact with one another.

Metal wires of a stacked inductor

Methods for bonding substrate surfaces, bonded substrate assemblies, and design structures for a bonded substrate assembly. Device structures of a product chip are formed using a first surface of a device substrate. A wiring layer of an interconnect structure for the device structures is formed on the product chip. The wiring layer is planarized. A temporary handle wafer is removably bonded to the planarized wiring layer. In response to removably bonding the temporary handle wafer to the planarized first wiring layer, a second surface of the device substrate, which is opposite to the first surface, is bonded to a final handle substrate. The temporary handle wafer is then removed from the assembly.

Flattened substrate surface for substrate bonding

Various embodiments include managing metal densities in kerf sections of an integrated circuit (IC) wafer. In some embodiments, a method includes: forming an integrated circuit (IC) wafer including a wafer kerf region, the wafer kerf region having a metal density of less than approximately 0.5 percent relative to a total density of the wafer kerf region.

Methods of managing metal density in dicing channel and related integrated circuit structures

Processes for improving adhesion of films to semiconductor wafers and a semiconductor structure are provided. By implementing the processes of the invention, it is possible to significantly suppress defect creation, e.g., decrease particle generation, during wafer fabrication processes. More specifically, the processes described significantly reduce flaking of a TaN film from edges or extreme edges (bevel) of the wafer by effectively increasing the adhesion properties of the TaN film on the wafer. The method increasing a mol percent of nitride with respect to a total tantalum plus nitride to 25% or greater during a barrier layer fabrication process.

Methods of manufacturing semiconductor devices and a semiconductor structure

Structures and design structures for improved adhesion of protective layers of imager microlens structures are disclosed. A method of fabricating a semiconductor structure includes forming an interfacial region between a microlens and a protective oxide layer. The interfacial region has a lower concentration of oxygen than the protective oxide layer.

Imager microlens structure having interfacial region for adhesion of protective layer

An Integrated Circuit (IC) and a method of making the same. In one embodiment, an integrated circuit includes: a substrate; a first metal layer disposed on the substrate and including a sensor structure configured to indicate a crack in a portion of the integrated circuit; and a second metal layer disposed proximate the first metal layer, the second metal layer including a wire component disposed proximate the sensor structure.

Integrated circuit including sensor structure, related method and design structure

Growing community of inventors

Jericho, VT, United States of America

Edward Crandal Cooney, Iii