Arm Limited

Synopsys, Inc.

Arc International

Edward Charles Plowman

Sean Tristram Ellis

Mohammed Noshad Khan

James Robert Howard Hakewill

Daren Croxford

Simon Andrew Ford

Jørn Nystad

Borgar Ljosland

Ben James

James Robert-Howard Hakewill

A data processing system comprises processing circuitry arranged to generate data to form an output array of data, processing circuitry arranged to store the generated data in an output bufferby writing compressed blocks of data representing particular regions of the output array of data to the output buffer, processing circuitryarranged to read a compressed block of data representing a particular region of the array of data from the output buffer, processing circuitryarranged to acquire meta-data from the compressed block of data, and processing circuitryarranged to process the block of data. The acquired meta-data is used to affect the processing of the block of data.

Data processing systems

When rendering a region of a three-dimensional object represented by a base set of polygon vertices in a graphics processing pipeline, a first processing stage uses meta-information representative of the surface relief of the region of the three-dimensional object to determine whether to generate a set of additional polygon vertices over the region of the three-dimensional object, and generates the additional set of polygon vertices (when this is deemed necessary). A second processing stage then uses information representative of the surface relief of the region of the three-dimensional object to modify the positions of one or more of the polygon vertices, before the vertices are assembled into primitives that are then rasterised and rendered.

Generating polygon vertices using surface relief information

In a tile-based graphics processing system, when a tile for a render output is to be generated, the fragment data storage requirements for each fragment to be generated for the tile is determined, and a color and/or depth buffer in the tile buffer is allocated for use by the fragments for the tile based on the determination. The graphics processing pipeline then, when generating rendered fragment data for the tile, stores the rendered fragment data in the color buffer and/or depth buffer of the tile buffer allocated to the fragments for the tile

Graphics processing systems

A method of managing the configuration, design parameters, and functionality of an integrated circuit (IC) design using a hardware description language (HDL). Instructions can be added, subtracted, or generated by the designer interactively during the design process, and customized HDL descriptions of the IC design are generated through the use of scripts based on the user-edited instruction set and inputs. The customized HDL description can then be used as the basis for generating 'makefiles' for purposes of simulation and/or logic level synthesis. The method further affords the ability to generate an HDL model of a complete device, such as a microprocessor or DSP. A computer program implementing the aforementioned method and a hardware system for running the computer program are also disclosed.

Managing the configuration and functionality of a semiconductor design

In a graphics processing system, when a fragment reaches a texturing stage, it is determined whether the texture to be applied is a static or dynamic texture. If it is determined that the required texels relate to a dynamic texture, then the system first tries to fetch those texels from a dynamic texture memory. If it is found that the texels are not available in the dynamic texture memory, then the relevant texels are generated in an 'on-demand' fashion and stored in the dynamic texture memory so that they can be applied to the fragment.

A shared memory is provided accessible by a central processing unit and a graphics processing unit. A bus is provided via which the central processing unit, graphics processing unit and shared memory communicate. A first mechanism controls the graphics processing unit and the central processing unit routes control signals via the bus. An interface is provided between the central processing unit and the graphics processing unit, and an additional mechanism controls the graphics processing unit and the central processing unit provides control signals over the interface. This enables the GPU to continue to be used to handle large batches of graphics processing operations loosely coupled with the operations performed by the CPU, and it is also possible to employ the GPU to perform processing operations on behalf of the CPU in situations where those operations are tightly coupled with the operations performed by the CPU.

Growing community of inventors

Gamlingay, United Kingdom

Edward Charles Plowman