Ncr Corporation

Cpu Technology, Inc.

Other

The Boeing Company

Edward C King

Alan G Smith

Fulps V Vermeer

Anton Goeppel

Pirmin L Weisser

Jackson L Ellis

Robert B Moussavi

Forrest O Arnold

Laszlo Hars

John Matthew Adams

Don Black

Daniel T Barber

Sterett Robertson

Paul J Lemmon

Gerhard Roehrl

V Thomas Powell

Scott Smith

Mark E Scheitrum

James C Lee

Jeffrey S Hammond

Georg Dollinger

Richard S Czyzewski

A system for providing high security for data stored in memories in computer systems is disclosed. A different encryption key is used for every memory location, and a write counter hides rewriting of the same data to a given location. As a result, the data for every read or write transaction between the microprocessor and the memory is encrypted differently for each transaction for each address, thereby providing a high level of security for the data stored.

Infinite key memory transaction unit

A simulation of an electronics system which performs a set of operations of interest. A simulated supervisory circuit detects a state in which all the operations have been completed, and also determines the amount of time until the occurrence of the next relevant event. Simulation time is then advanced by that amount of time. This enables simulation time corresponding to an inactive system to be eliminated.

Automatic time warp for electronic system simulation

A pest control system includes pest control devices installed about an area or building. These devices each include a bait member and a wireless communication circuit. The wireless communication circuit may be in the form of a passive RF tag that transmits information indicative of bait status and an identifier unique to each pest control device. The wireless communication circuit can be configured in a first assembly for detecting the presence of one or more pests and a second assembly for delivering a pesticide once pests are detected. The assemblies are interchangeable within a pest control device housing. The wireless communication circuit is connected to a sensor having an electrically conductive element that can be comprised of a nonmetallic material, such as a carbon-based ink. One or more connection members electrically couple the wireless communication circuit and the sensor. These members are comprised of an electrically conductive, elastomeric compound, such as a carbon-filled silicone rubber.

Pest control apparatus and methods

A computer memory system connectable to a processor and having programmable operational characteristics based on characteristics of the processor. The memory system includes several caches and a main memory connected to a bus. One cache can be programmed to store only code data. Another cache can be programmed to buffer data writes to the main memory only from the processor. The main memory supports fast page mode and can be programmed to selectively reopen either code or non-code data pages.

Computer memory system having programmable operational characteristics

A computer system simulator concurrently models both processor operation and signal logic behavior and provides a high degree of user interaction and flexibility in the observation and control of signal values and memory contents during the execution of a simulation. During simulation, source equations for signals can be requested for display either through direct input of a signal name or through graphical interface with the simulation display. Signal equations can in this manner be traced back through several levels, which conveniently provides important information during the observation and modification of signal values. Memory areas may be associated with a processor and loaded with data to be executed by that processor during the simulation. The data can be displayed in both numerical and assembly code mnemonic form, and may also be modified by entering numbers or assembly instructions. The simulated processor execution may thus be interactively modified during the simulation. Additionally, the ability to step the simulation backwards through time, and then forward again, is provided.

Method and apparatus for interactively displaying signal information

The present invention provides for a computer system having a plurality of parallel processor units with each processor unit associated with at least one register for receiving data for the processor unit. The computer system has a bus unit, coupled to the output of each processor unit and the associated register of each processor unit, to transfer the output data of a first processor unit into an associated register of a second processor unit in a single computer operation. The second processor unit is prevented from reading the associated register until the bus unit transfers the output data from the first processor unit to the second processor unit.

High speed, direct register access operation for parallel processing

A statistically fast, high performance computer memory system including a system memory for storing code and non-code data accessible by at least two bus masters, a bus connecting the memory with the bus masters, and a plurality of caches connected to the bus. An internal cache holds data selected solely on the basis of memory accesses by the host processor, a pre-fetch cache pre-fetches code from the memory, and a write buffer cache connected to the bus for buffering data written to the memory.

Memory system with write buffer, prefetch and internal caches

The present invention provides for a computer system having a plurality of parallel processor units. The processor units are connected in common to a signal line with each processor capable of setting a first signal level on the line and monitoring the line in response to instructions to the processor. This allows each processor unit to be notified of the completion of a parallel operation by other participating processor units upon a second signal level on the signal line. More than one signal lines may be connected between the parallel processor units to provide synchronization of different parallel operations between different processor units.

Multiprocessors system for selectively wire-oring a combination of

A parallel processing system is provided with a plurality of processors and a plurality of memories, and bus units with arbitration coupling the processors and memories. A bus unit provides a pathway between one processor and the bus unit's respective memory. Each bus unit arbitrates multiple simultaneous access requests for its respective memory and communicates its decisions to other bus units so that a memory access requiring multiple memories will only occur if all those memories are available. The coupling of processors to memories can change, dynamically, each bus cycle without the need for setup before the bus cycle either by pipelining or having unused bus cycles. In a specific embodiment, the memory access information is provided on high order address lines, where the processor logically accesses different memory address spaces to make different accesses, thereby sharing memory with other processors.

Dynamic bus reconfiguration logic

A method and system for managing data elements in a memory system. The memory system is accessible by a plurality of bus masters connected by a bus to the system. Code data elements to be read are predicted. The predicted code data elements are then transferred within the memory system from a slow to high speed memory without delaying memory access requests for data from the bus masters.

System and method for enhancing computer operation by prefetching data

An interface circuit and method for transferring data between first and second buses. The circuit includes a buffer having a plurality of registers and write and read means. The write means stores data words received from the second bus in non-sequential registers. The read means transfers the data words from sequential registers to the first bus.

Work station or similar data processing system including interfacing

A computer system having a plurality of parallel processor units with each processor unit having an output bus of n bits and an associated mask register is provided. The computer system comprises a bus unit, coupled to the output bus of each processor unit and each associated mask register, for masking the output bus bits with bits in the mask register of each processor unit and logically combining the resulting masked bits from each processor unit into an output bus of n bits in one computer operation.

High speed mask and logical combination operations for parallel

An architecture and method for operating a work station. The work station includes a CPU, a bus interface unit and a control line. The CPU is selected from a group of CPUs differing in certain operational parameters. The bus interface circuit is connected between an external bus and the CPU. The control line is connected to the interface circuit and provides a signal indicating the type of CPU connected to the circuit.

Work station architecture with selectable CPU

The invention is a system and method for accessing a plurality of memory banks. The system includes a number of memory banks, a register and a controller. The register stores capacity information of each memory bank. The controller is connected to the register and memory banks and uses the capacity information to determine whether or not addresses are to be interleaved between a pair of memory banks. If the memory banks are of similar capacities, the addresses may be interleaved therebetween.

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Fremont, CA, United States of America

Edward C King