Motorola Corporation

Edward C Hepworth

Rodney J Means

Charles I Peddle

Michael F Wiles

Thomas H Bennett

William D Mensch, Jr

Earl F Carlow

Rodney H Orgill

Wilbur L Mathys

Shikun Kyu

Gene A Schriber

Thomas C Daly

A bit-oriented data link controller provides the interface between a microcomputer or terminal and a data communications link. The data link controller is capable of accommodating the three most commonly available bit-oriented data link control protocols, namely SDLC, HDLC, and ADCCP. The data link controller provides the data communications interface for both primary and secondary stations in stand-alone, polling, and loop configurations.

Advanced data link controller having a plurality of multi-bit status

Control circuitry for data transfer in an advanced data link controller

Advanced data link controller

A digital logic circuit provides character framing for a continuous stream of synchronous serial data characters. The digital logic circuit includes a shift register arranged for serial loading and parallel unloading of the received serial data characters. The parallel unloading of a received character triggers control logic to force a control code prefix consisting of a series of logical '1's with a trailing logical '0' into the individual shift register stages. Serial loading of the next serial data character results in successive shifts of the control code prefix through the shift register stages. Serial loading continues until the trailing logic '0' shifts into a 'shift register full' stage and is detected by the control logic. Detection of a change of state in the 'shift register full' stage causes parallel unloading of the received serial data character followed by another forcing of the control code prefix to reinitiate the parallel unloading sequence.

Character framing circuit

A digital system including a plurality of metal-oxide-semiconductor (MOS) chip random access memories (RAM), read only memories (ROM) and peripheral interface adaptors coupled to a common bidirectional data bus which is coupled to and controlled by a microprocessor unit (MPU). Each peripheral interface adaptor includes a control register loadable under program control. The contents of the control register control selection of several registers within the interface adaptor. The control register also controls other functions of the peripheral interface adaptor, including determining direction of data movement at the peripheral buffers of the interface adaptor. The contents of the control register of each interface adaptor are monitorable by the microprocessor unit.

Digital data processing system with interface adaptor having

A bit-oriented data link controller provides the interface between a microcomputer or terminal and a data communications link. The data link controller is capable of accommodating the three most commonly available bit-oriented data link control protocols, namely Synchronous Data Link Control SDLC, High Level Data Link Control HDLC, and Advanced Data Communications Control Procedure ADCCP. The data link controller provides the data communications interface for both primary and secondary stations in stand-alone, polling, and loop configurations.

A data processing system in which a central processor polls one or more peripheral devices to initiate a data transfer or to enable a data transfer. The system includes logic associated with a peripheral device or with an interface device for sensing the occurrence of data handling errors such as parity errors, carrier loss, clear to send loss, data overrun or underflow, and for interrupting the central processor upon such occurrence to avoid polling that peripheral device unnecessarily. A status signal is also generated to inform the processor of the nature of the interrupt, so as to distinguish from, for example, the interrupt of another device which is operative to communicate by means of such interrupt rather than by polling.

Error driven interrupt for polled MPU systems

A peripheral interface adaptor (PIA) circuit for data processing systems contains memory elements or control registers allowing modification under program control of the logical functions of the PIA. The peripheral interface adaptor includes a plurality of system data bus buffer circuits coupled to a system data bus and further includes peripheral interface buffer circuits coupled to a bidirectional peripheral data bus. The direction of data flow in the peripheral data bus is controlled by a data direction register. Data from the system data bus buffer is entered into an input register, and is transferred from there to an input bus coupled to the control register, a data direction register and a data register. Data from the peripheral data bus, the data direction register and the control register are transferred via an output bus to the system data bus buffers. Control signals are generated by select, read/write control, and register select logic which provides signals on a control bus coupled to the input register, the data register, the control register, and the data direction register to control data transfers between the various buses, registers, and buffer circuits.

Interface adaptor architecture

An interface adaptor couples peripheral equipment to a bidirectional data bus and an address bus of a digital system. A plurality of interrupt sources are provided on such an interface adaptor circuit. A status bit in a status register of the interface adaptor is provided which contains a logical state indicative of a logical ORing of the plurality of interrupt sources on the interface adaptor circuit.

Interrupt status indication logic for polled interrupt digital system

A first-in-first-out memory system is described in which the storage array is made up of single rank storage elements. Control logic means provide for sequencing the transfer of data within the storage array such that transfer can occur only between adjacent groups of storage elements for which a status record shows an empty data word preceded by a full data word.

First-in-first-out register implemented with single rank storage elements

A digital system includes a microprocessor coupled to a data bus and an address bus. A memory for storing data and instructions is connected to the data bus and the address bus. A peripheral device is connected to an interface adaptor. The interface adaptor is connected to the data bus and the address bus, and performs the function of interfacing between the digital system and a peripheral device, such as a printer or a display device. The microprocessor includes logic circuitry for generating a Valid Memory Address (VMA) output. The VMA output is used to generate an enable signal applied to the memory and the adaptor to enable the memory and the adaptor to be accessed by the microprocessor when the binary address on the address bus is valid and to prevent the memory and the adaptor from being accessed by the microprocessor when the binary address on the address bus is not valid with respect to the microprocessor.

Valid memory address enable system for a microprocessor system

A microprocessor system includes a microprocessor, a memory, and an interface adaptor all coupled to a data bus. The interface adaptor is coupled between the data bus and a peripheral device, such as a teleprinter. A first interrupt conductor is connected to the peripheral device and to interrupt logic circuitry in the interface adaptor. A second interrupt conductor is connected to the microprocessor and the interrupt logic circuitry. The interrupt logic circuitry is also coupled to and interrogatable by the microprocessor via the data bus. The interrupt logic circuitry stores interrupt contrl information from the data bus, and generates a second interrupt signal on the second interrupt conductor in response to the stored interrupt control information and an interrupt signal generated on the first interrupt conductor by the peripheral device. The interrupt logic circuitry also stores status information indicative of the occurrence of the first interrupt signal and effects interrogation of that status via the data bus.

Interrupt system for microprocessor system

An integrated circuit synchronous data adaptor (SSDA) provides a bidirectional interface for synchronous data interchange. Internal control and interface logic including first-in-first-out (FIFO) buffer memory enables simultaneous transmitting and receiving of standard synchronous communication characters to allow data transfer between serial data channels and the parallel bidirectional data bus of a bus organized system such as a microprocessor (MPU) system. Parallel data from the bus system is serially transmitted and received by the SSDA with synchronization character insertion and deletion, fill character insertion and deletion, parity generation and error checking. The functional configuration of the SSDA is programmed via the MPU system data bus during system initialization and can be reconfigured via program control during subsequent system operation. Programmable control registers provide control for variable word lengths, transmit control, receive control, synchronization control, and interrupt control. Status, timing and control lines provide peripheral unit or modem control.

Synchronous serial data adaptor

A digital logic circuit synchronizing data transfers between asynchronously clocked data systems. Synchronization is accomplished by three logically interlocked storage elements which respectively record and control (1) the time when data is available for transfer, (2) time when data transfer begins and (3) the time when data transfer is complete. Transfer is accomplished without a loss of data independent of the clock pulse width and frequency relationship of the asynchronously clocked systems.

Data transfer synchronizing circuit

An interface adaptor suitable for use in a microprocessor system includes an input register coupled to a bidirectional data bus of the microprocessor system. The interface adaptor includes a plurality of registers, including a control register and a data register, coupled to the input register by means of an internal input bus. Each of the plurality of registers includes flip-flops which are coupled as slave flip-flops to corresponding flip-flops of the input register. The corresponding flip-flops of the input register function as master flip-flops. The interface adaptor also includes register selection logic circuitry for selecting one of the plurality of registers by electrically coupling its slave flip-flop to the corresponding master flip-flops of the input register.

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Apache Junction, AZ, United States of America

Edward C Hepworth