International Business Machines Corporation

Edward C Fredericks

Giorgio G Via

Madan M Nanda

Louis L Hsu

Wayne Martin Moreau

David Edward Kotecki

Klaus D Beyer

Christopher Carr Parks

Harish N Kotecha

Ming-Fea Chow

George T Chiu

John F Conway

Herbert L Greenhaus

A method of providing sublayer contacts in vertical walled trenches is proposed. In accordance with the present invention, the phosphorus doped amorphous silicon is deposited at temperatures less than 570.degree. C. The conversion into the extremely large crystal low resistivity polysilicon is accomplished by a low temperature anneal at 400.degree. C. to 500.degree. C. for several hours and a short rapid thermal anneal (RTA) treatment at a high temperature approximately 850.degree. C. for twenty seconds. These two conversion heat treatments are done at sufficiently low thermal budget to prevent any significant dopant movement within a shallow junction transistor. After anneal, the excess low resistivity silicon is planarized away by known techniques such as chemical/mechanical polishing. In addition, due to the trench filling abilities of the amorphous silicon CVD process, in one preferred embodiment of the invention the capability of accessing subsurface silcon layers at different trench depths is demonstrated.

Sub-layer contact technique using in situ doped amorphous silicon and

An apparatus and method for characterizing lithography imaging to quickly optimize a lithography process is described. The apparatus consists of two lithography masks for use with an optical stepper, ion-beam or x-ray lithography tool. The first mask is used for creating topography on the wafer substrate, and is patterned with groups of large elements arranged in orthogonal and angular directions. The second mask is used for defining a periodic pattern over the large elements. Preferably, the periodic pattern is in the same order of dimension as the critical element on the integrated circuit. A method is provided for characterizing lithography tools which do not have lithography masks such as an electron beam exposure tool.

Lithography imaging tool and related photolithographic processes

A method which provides for a permanent planarization layer on a multilayer integrated circuit. The planarization layer resides above other circuit layers which reflect incident light. A layer of photoresist is formed over the planarization layers and imaged through a mask with circuit defining structure. During exposure of the photoresist, incident light passes through the planarization layer. Scattering from the boundary of the planarization layer and photoresist is minimized because the index of refraction of the planarization layer is substantially equal to the index of refraction of the photoresist. Light reflected from the underlaying layers is substantially absorbed by the planarization layer. Reduction of the reflected and scattered light results in improved resolution of developed images in photoresist. The developed images, when further processed into interconnecting conductors have improved definition, avoiding the additional process steps of applying a temporary dye or other light impervious layer.

Method for improving resolution in microelectronic circuits using

In a photoresist lift-off process for depositing metal on a semiconductor substrate, a protective coating of silicon is applied to an etched via hole prior to the metal deposition step. This prevents the formation of contaminant trapping voids and contaminated chemical residues which would otherwise occur at the base of the metal line subsequently deposited in the bottom of the via hole. The protective silicon layer, which has a thickness of from 100 to 300 angstroms, remains intact as a permanent part of the structure.

Semiconductor contact protection

A photoresist photolithographic process is disclosed which provides for a single development step to develop a dual layer photoresist for lift-off, reactive ion etching, or ion implantation processes requiring a precise aperture size at the top of the photoresist layer. The process involves the deposition of two compositionally similar layers, with the first layer having the characteristic of being soluble in a developer after exposure to light and baking, and the second layer having the characteristic of being insoluble in the same developer after having been exposed to light and baked. With these two distinct characteristics for the two layers of photoresist, the effective aperture for windows in the composite photoresist can be tightly controlled in its cross-sectional dimension in the face of large variations in the developer concentration and development time.

Multi-level resist image reversal lithography process

A method making self-aligned semiconductors utilizing two resist masking steps to form a device; making one of the masks insoluable with respect to the other so that when a first part of the device is formed by a first mask, and a second part of the device is formed by the second masks, the parts are self-aligned when the first resist is dissolved.

Photoresist lift-off process for fabricating semiconductor devices

A resist system for semiconductor device fabrication comprised of bottom positive resist layer of a diazoquinone/novolak resist applied to a substrate and overcoated with a like or different diazoquinone/novolak top resist layer which has been sensitized with pyrene and/or its derivatives.

Process for forming resist masks utilizing O-quinone diazide and pyrene

Resist images are hardened so that they are flow resistant at elevated temperatures by coating the image with a layer of a quinone-diazide hardening agent and heating the image to cause the agent to react with the resist and form a hardened image.

Resist image hardening process

A positive relief image is produced by coating a substrate with a layer of a copolymer containing about 90-98 mole percent of polymerized lower alkyl methacrylate units and about 2-10 mole percent of polymerized lower haloalkyl methacrylate units, heating the layer to cause cross-linking between polymer chains by removal of hydrogen halide, patternwise exposing the layer with high energy radiation such as a scanning electron beam, and removing the exposed portion of the layer with a solvent developer. The purpose of this abstract is to enable the public and the Patents and Trademark Office to rapidly determine the subject matter of the technical disclosure of the application. This abstract is neither intended to define the invention of the application nor is it intended to be limiting as to the scope thereof.

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Haymarket, VA, United States of America

Edward C Fredericks