Agere Systems Inc.

Agere Systems Guardian Corp.

Lsi Corporation

Edward Belden Harris

Sailesh Mansinh Merchant

Stephen Ward Downey

Kurt George Steiner

Yifeng Winston Yan

Che Choi Leung

Susan Clay Vitkavage

Bruce W McNeill

Canzhong He

Simon John Molloy

Nace Layadi

Sidhartha Sen

Bonnie E Weir

Frank Yauchee Hui

Richard Joseph McPartland

Wayne E Werner

Ramnath Venkatraman

Ross Alan Kohler

Sylvia Thomas

Michael Scott Carroll

Richard William Gregor

Tony G Ivanov

Paul B Murphey

Joseph J Check

Lyle K Mantz, Ii

Richard R Kiser

Richard Hogg

Patricia J Leith

Michael Jay Parrish

Richard J Mcpartland

A chip and a method of fabricating the chip for low cost chip identification circuitry. In one embodiment, a method of manufacturing an integrated circuit includes formation of a multi-level metallization structure including a pad level comprising programming pads. A plurality of active devices are formed on a substrate, and multiple levels of metallization are formed over the active devices, connecting some of the active devices to form programmable circuitry. The programmable circuitry is connected to pairs of programming pads on the bond pad level. Programming pads in some of the pairs are selectively connected to one another by using conductive ink deposited with maskless inkjet printing techniques. The pads are then covered with a non-conductive protective layer.

Method of identifying and/or programming an integrated circuit

An IC capacitor bank includes a plurality of high-k metal-insulator-metal (MIM) capacitors connected to a pair of conductive traces. A fusible trace located on an end of one of the pair of conductive traces forms a capacitor column connected between supply lines, such that failure of a dielectric in the MIM capacitors causes the fusible trace to at least partially open thereby limiting a fault current in the capacitor column. Additionally, a method of manufacturing an IC capacitor bank includes providing a plurality of high-k metal-insulator-metal (MIM) capacitors connected to a pair of conductive traces and locating a fusible trace on an end of the pair of conductive traces to form a capacitor column that is connected between supply lines, such that failure of a dielectric in the MIM capacitors causes the fusible trace to at least partially open thereby limiting a fault current in the capacitor column.

Mitigation of detrimental breakdown of a high dielectric constant metal-insulator-metal capacitor in a capacitor bank

A random number generator circuit includes a first memory having multiple storage elements. Each of the storage elements has an initial state corresponding thereto when powered up by a voltage supply source applied to the first memory. The first memory is operative to generate a first signal including multiple bits indicative of the respective initial states of the storage elements. The random number generator circuit further includes an error correction circuit coupled to the first memory. The error correction circuit is operative to receive the first signal and to correct at least one bit in the first signal that is not repeatable upon successive applications of power to the first memory to thereby generate a second signal. The second signal is a random number that is repeatable upon successive applications of power to the first memory.

Secure random number generator

An IO interface circuit for use in a high voltage tolerant application is provided. The IO interface circuit includes a signal pad and at least a first parasitic bipolar transistor having an emitter adapted for connection to a voltage return of the interface circuit, a base adapted to receive a first control signal, and a collector connected directly to the signal pad in an open collector configuration. The interface circuit further includes a MOS control circuit coupled to the parasitic bipolar transistor and being operative to generate the first control signal. The IO interface circuit may further include an active pull-up circuit connected between a voltage supply of the interface circuit and the signal pad.

High voltage tolerant input/output interface circuit

An integrated circuit (IC) structure includes a semiconductor substrate having a plurality of memory bits including IC identification information and a plurality of alternating metal and via layers thereabove. The IC structure includes a bond pad layer formed over a top one of the metal layers. The bond pad layer includes a plurality of pins connected to respective ones of the plurality of memory bits through the metal and via layers, at least one first pad connected to a higher voltage power supply rail and at least one second pad is connected to a lower voltage power supply rail. The bond pad layer has a plurality of circuit segments therein that each connects a respective one of the plurality of pins to either the at least one first pad or the at least one second pad for programming the IC identification information into the memory bit corresponding to that pin.

Chip identification using top metal layer

Provided is a method for separating a semiconductor wafer into individual semiconductor dies. The method for separating the semiconductor wafer, among other steps, may include implanting an impurity into regions of a semiconductor wafer proximate junctions where semiconductor dies join one another, the impurity configured to disrupt bonds in the semiconductor wafer proximate the junctions and lead to weakened regions. The method for separating the semiconductor wafer may further include separating the semiconductor wafer having the impurity into individual semiconductor dies along the weakened regions.

Method for separating a semiconductor wafer into individual semiconductor dies using an implanted impurity

A method for increasing a voltage tolerance of a MOS device having a first capacitance value associated therewith is provided. The method includes the steps of: connecting at least a first capacitor in series with the MOS device, the first capacitor having a first capacitance value associated therewith, the first capacitor having a first terminal coupled to a gate of the MOS device and a second terminal adapted to receive a first signal; and adjusting a ratio of the first capacitance value and a second capacitance value associated with the MOS device such that a second signal present at the gate of the MOS device will be an attenuated version of the first signal. An amount of attenuation of the first signal is a function of the ratio of the first and second capacitance values.

High voltage tolerant metal-oxide-semiconductor device

In an illustrative embodiment, a memory cell comprises a first and a second MOSFET, wherein the first MOSFET undergoes a process to modify the threshold voltage such that a modified threshold voltage represents a first stored logic value. By determining which one of the first and the second MOSFETs has an altered threshold voltage, the stored logic value is determinable. The threshold voltage of the first MOSFET is altered by supplying current through a MOSFET gate, causing a gate heating effect that results in a threshold voltage shift.

Method and apparatus for storing data in a write-once non-volatile memory

An electronic pressure-sensing devicecomprising a transistorlocated on a substrate. The device also comprises a linker armthat has a tipwhich is configured to touch a contact regionof the substrate that is near the transistor. The device also comprises a pressure converterthat is mechanically coupled to the linker arm. The pressure converter is configured to cause, in response to a pressure change, the tip to impart a force capable of changing an electrical conductivity of the transistor.

Electronic pressure-sensing device

The specification describes matched capacitor pairs that employ interconnect metal in an interdigitated form, and are made with an area efficient configuration. In addition, structural variations between capacitors in the capacitor pair are minimized to provide optimum matching. According to the invention, the capacitor pairs are interdigitated in a manner that ensures that the plates of each pair occupy common area on the substrate. Structural anomalies due to process conditions are compensated in that a given anomaly affects both capacitors in the same way. Two of the capacitor plates, one in each pair, are formed of comb structures, with the fingers of the combs interdigitated. The other plates are formed using one or more plates interleaved between the interdigitated plates.

Interdigitated capacitors

An inductor formed within an integrated circuit and a method for forming the inductor. The inductor comprises an underlying layer of aluminum formed in a first metallization layer and patterned and etched into the desired shape. In one embodiment the aluminum line comprises a spiral shape. According to a damascene process, a conductive runner, preferably of copper, is formed in a dielectric layer overlying the aluminum line and in electrical contact therewith. The aluminum line and the conductive runner cooperate to form the inductor. In another embodiment the aluminum line and the conductive runner are formed in a vertically spaced-apart orientation, with tungsten plugs or conductive vias formed to provide electrical connection therebetween. A method for forming the inductor comprises forming an aluminum conductive line and forming a conductive runner over the conductive line.

Inductor formed in an integrated circuit

An apparatus and method for forming a write-once non-volatile memory cell. A memory cell comprises a first and a second MOSFET, wherein the first MOSFET undergoes a process to modify the threshold voltage such that a modified threshold voltage represents a first stored logic value. By determining which one of the first and the second MOSFETS has an altered threshold voltage, the stored logic value is determinable. The threshold voltage of the first MOSFET is altered by supplying current through a MOSFET gate, causing a gate heating effect that results in a threshold voltage shift.

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Fogelsville, PA, United States of America

Edward Belden Harris