Altera Corporation

Edward Aung

Rakesh H Patel

Chong H Lee

John E Turner

Henry Y Lui

Paul Butler

Chiakang Sung

Richard G Cliff

Greg W Starr

Robert R N Bielby

Gregory W Starr

Richard Yen-Hsiang Chang

Gregg Starr

A programmable logic device ('PLD') is augmented with programmable clock data recover ('CDR') circuitry to allow the PLD to communicate via any of a large number of CDR signaling protocols. The CDR circuitry may be integrated with the PLD, or it may be wholly or partly on a separate integrated circuit. The circuitry may be capable of CDR input, CDR output, or both. The CDR capability may be provided in combination with other non-CDR signaling capability such as non-CDR low voltage differential signaling (&#x201c;LVDS&#x201d;). The circuitry may be part of a larger system.

Clock data recovery circuitry associated with programmable logic device circuitry

In one aspect, an embodiment provides a clock loss sense and switchover circuit and method in which clock switchover is responsive to loss of a primary signal and to additional switch command signaling. In another aspect, an embodiment provides a clock loss sense circuit and method that utilizes counters and reset signals to compare a primary clock and secondary clock signal.

Clock loss detection and switchover circuit

A PLL circuit is described. The PLL circuit includes: a signal generator and at least one divider coupled to the signal generator, where the at least one divider is programmable in user mode. In one embodiment, the PLL circuit includes a memory device associated with the at least one divider, where the memory device receives settings data and provides settings data to the at least one divider in user mode.

Phase locked loop (PLL) and delay locked loop (DLL) counter and delay element programming in user mode

A programmable logic device is provided with phase-locked loop (&ldquo;PLL&rdquo;) circuitry that includes two serially connected PLL circuits. An input clock signal is processed by a first of the PLL circuits to produce an intermediate clock signal having a frequency different from the input clock signal frequency. The intermediate clock signal is processed by the second PLL circuit to produce a final modified clock signal having a frequency different from both the input clock signal frequency and the intermediate clock signal frequency. By providing two serially connected PLL circuits, each PLL circuit can be required to operate with frequencies in a narrower range than might otherwise be required in a single PLL circuit required to produce a given input-to-final frequency change. Other circuitry on the programmable logic device (e.g., input/output registers and programmable logic circuitry for processing data signals) is responsive to the input and final modified clock signals. The two PLL circuits may alternatively be used separately or partly separately.

Phase-locked loop circuitry for programmable logic devices

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San Leandro, CA, United States of America

Edward Aung