International Business Machines Corporation

Edward Armayor McQuade

Derek E Williams

Chung-Lung K Shum

Viresh Paruthi

Wolfgang Roesner

Stephen Gerard Shuma

Robert Alan Cargnoni

Michael H Wood

Alvan Wing Ng

Benedikt Geukes

Ali S El-Zein

Klaus-Dieter Schubert

A first plurality of hardware description language (HDL) files describe a hierarchical integrated circuit design utilizing a simplified HDL syntax that omits specification of logical clock connections for at least some entities in the hierarchical integrated circuit design. The hierarchical integrated circuit design as described by the first plurality of HDL files is processed to automatically add logical clock connections for entities in the hierarchical integrated circuit design for which specification of logical clock connections are omitted in the first plurality of HDL files. Based on the processing, a second plurality of HDL files defining the hierarchical integrated circuit design is generated.

Logical clock connection in an integrated circuit design

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Katonah, NY, United States of America

Edward Armayor McQuade