Nvidia Corporation

Lineage Biosciences, Inc.

Facebook Technologies, LLC

Other

Edward Anthony Hutchins

Michael J M Toksvig

Brian K Angell

Justin Michael Mahan

Christopher D S Donham

Gary C King

Paul Kim

Tyson J Bergland

Brian Keith Cabral

Hei-Mun Christina Fan

Craig M Okruhlica

James T Battle

Steven E Molnar

Mark J Kilgard

Alexander Lev Minkin

Douglas Sim Dietrich

Volga Aksoy

Benjamin J Garlick

Dean Joseph Beeler

Paul Louis Pedriana

Cass Watson Everitt

Ming Benjamin Zhu

Douglas A Voorhies

Bryon S Nordquist

Bruce Holmer

Matthew J Craighead

Ashok Srinivasan

William T Warner

Kevin P Acken

Scott C Heeschen

Ewa Kubalska

Sanjay O Gupta

Christopher Donham

George E Scott, Iii

Mark Tian

George Easton Scott Iii

Christopher J Mills

Jim Battle

Sekhar Nori

The invention relates to methods of tagging analytes in a sample.

Methods and compositions for tagging and analyzing samples

The disclosed computer-implemented method may include (1) receiving a first 2D frame depicting an evolving 3D scene and elements in the evolving 3D scene, (2) receiving a second 2D frame depicting the evolving 3D scene and the elements, (3) deriving 2D motion vectors from the first 2D frame and the second 2D frame that each include an estimated offset from coordinates of an element in the first 2D frame to coordinates of the element in the second 2D frame, (4) receiving depth information for the evolving 3D scene, (5) using the 2D motion vectors and the depth information to extrapolate a synthetic 2D frame, and (6) displaying the synthetic 2D frame to a user. Various other methods, systems, and computer-readable media are also disclosed.

Systems and methods for using depth information to extrapolate two-dimensional images

Systems and methods for using depth information to extrapolate two-dimentional images

A method in system for latency buffered scoreboarding in a graphics pipeline of a graphics processor. The method includes receiving a graphics primitive for rasterization in a raster stage of a graphics processor and rasterizing the graphics primitive to generate a plurality pixels related to the graphics primitive. An ID stored to account for an initiation of parameter evaluation for each of the plurality of pixels as the pixels are transmitted to a subsequent stage of the graphics processor. A buffer is used to store the fragment data resulting from the parameter evaluation for each of the plurality of pixels by the subsequent stage. The ID and the fragment data from the buffering are compared to determine whether they correspond to one another. The completion of parameter evaluation for each of the plurality of pixels is accounted for when the ID and the fragment data match and as the fragment data is written to a memory.

Scoreboard cache coherence in a graphics pipeline

An efficient pipeline debug statistics system and method are described. In one embodiment, an efficient pipeline debug is utilized in a graphics processing pipeline of a handheld device. In one embodiment, a pipeline debug statistics system includes a plurality of pipeline stages with probe points, a central statistic component, and a debug control component. The plurality of pipeline stages with probe points perform pipeline operations. The central statistic block gathers information from the probe points. The debug control component directs the gathering of information from the probe points. In one exemplary implementation, debug control component can direct gathering of information at a variety of levels and abstraction.

Pipeline debug statistics system and method

A method for loading a shader program from system memory into GPU memory. The method includes accessing the shader program in system memory of a computer system. A DMA transfer of the shader program from system memory into GPU memory is performed such that the shader program is loaded into GPU memory in an address independent manner.

Address independent shader program loading

Briefly, in accordance with one or more embodiments, a reconfigurable 3D graphics processor includes a pipeline configuration manager, a rasterizer, and a memory coupled to the triangle rasterizer. The pipeline configuration manager is capable of configuring the graphics processor to operate in a direct rasterizing mode or a tiling mode to process a sequence of drawing commands received from a processing unit.

Reconfigurable 3D graphics processor

Early Z scoreboard tracking systems and methods in accordance with the present invention are described. Multiple pixels are received and a pixel depth raster operation is performed on the pixels. The pixel depth raster operation comprises discarding a pixel that is occluded. In one exemplary implementation, the depth raster operation is done at a faster rate than a color raster operation. Pixels that pass the depth raster operation are checked for screen coincidence. Pixels with screen coincidence are stalled and pixels without screen coincidence are forwarded to lower stages of the pipeline. The lower stages of the pipeline are programmable and pixel flight time can vary (e.g., can include multiple passes through the lower stages). Execution through the lower stages is directed by a program sequencer which also directs notification to the pixel flight tracking when a pixel is done processing.

Early Z scoreboard tracking system and method

An apparatus is disclosed. The apparatus comprises an instruction mapping table, which includes a plurality of instruction counts and a plurality of instruction pointers each corresponding with one of the instruction counts. Each instruction pointer identifies a next instruction for execution. Further, each instruction count specifies a number of instructions to execute beginning with the next instruction. The apparatus also has a data operation unit adapted to receive a data group and adapted to execute on the received data group the number of instructions specified by a current instruction count of the instruction mapping table beginning with the next instruction identified by a current instruction pointer of the instruction mapping table before proceeding with another data group.

Reducing instruction execution passes of data groups through a data operation unit

Sourcing immediate values from a very long instruction word includes determining if a VLIW sub-instruction expansion condition exists. If the sub-instruction expansion condition exists, operation of a portion of a first arithmetic logic unit component is minimized. In addition, a part of a second arithmetic logic unit component is expanded by utilizing a block of a very long instruction word, which is normally utilized by the first arithmetic logic unit component, for the second arithmetic logic unit component if the sub-instruction expansion condition exists.

Techniques for sourcing immediate values from a VLIW

A rasterizer stage configured to implement multiple interpolators for graphics pipeline. The rasterizer stage includes a plurality of simultaneously operable low precision interpolators for computing a first set of pixel parameters for pixels of a geometric primitive and a plurality of simultaneously operable high precision interpolators for computing a second set of pixel parameters for pixels of the geometric primitive. The rasterizer stage also includes an output mechanism coupled to the interpolators for routing computed pixel parameters into a memory array. Parameters may be programmably assigned to the interpolators and the results thereof may be programmably assigned to portions of a pixel packet.

Method and system for implementing multiple high precision and low precision interpolators for a graphics pipeline

A present invention pixel processing system and method permit complicated three dimensional images to be rendered with shallow graphics pipelines including reduced gate counts and facilitates power conservation by utilizing a single unified data fetch stage (e.g., unified data fetch module) that retrieves a variety of different pixel surface attribute values (e.g., depth, color, and/or texture values) in a single stage. Different types of pixel surface attribute data (e.g., depth, color, texture) associated with multiple graphics processing functions (e.g., color blending, texture mapping, etc.) are retrieved in the single unified data fetch graphics pipeline stage. The pixel surface attribute values may be placed in corresponding variable fields of a pixel packet row. The pixel packet rows including the pixel surface attribute values are forwarded to downstream graphics pipeline stages (e.g., an arithmetic logic pipestage).

Unified data fetch graphics processing system and method

Detailed herein are approaches to enabling conditional execution of instructions in a graphics pipeline. In one embodiment, a method of conditional execution controller operation is detailed. The method involves configuring the conditional execution controller to evaluate conditional test. A pixel data packet is received into the conditional execution controller, and evaluated, with reference to the conditional test. A conditional execution flag, associated with the pixel data packet, is set, to indicate whether a conditional operation should be performed on the pixel data packet.

Conditional execution flag in graphics applications

Growing community of inventors

Mountain View, CA, United States of America

Edward Anthony Hutchins