Icera, Inc.

Graphcore Limited

Edward Andrews

Carlo Luschi

Jonathan Wallington

Alan Graham Alexander

Stephen Felix

Simon Christian Knowles

Mrudula Gore

Simon Huckett

Richard Luke Southwell Osborne

Peter Hedinger

Stephen Alan Allpress

Godfrey Da Costa

Simon Nicholas Walker

Colman Hegarty

Badreddine Noune

Dominic Alexander Masters

Jonathan Peter Lucas

Laolu Lijofi

Sam Chesney

A processing device comprising: a control register configured to store a scaling factor; at least one execution unit configured to execute instructions to perform arithmetic operations on input floating-point numbers provided according to a first floating-point format, wherein each of the input floating-point numbers provided according to the first floating-point format comprises a predetermined number of bits, wherein the at least one execution unit is configured to, in response to execution of an instance of a first of the instructions: perform processing of a first set of the input floating-point numbers to generate a result value, the result value provided in a further format and comprising more the predetermined number of bits, enabling representation of a greater range of values than is representable in the first floating-point format; and apply the scaling factor specified in the control register to increase or decrease an exponent of the result value.

Processing device for intermediate value scaling

A new type of instruction and a control register for the new type of instruction are provided to handle data that may be misaligned in memory. A first part of data (which may be misaligned in memory) is loaded into a first set of registers by loading a first atom containing the first part of data into registers. The pack instruction is executed by an execution unit to place part of data (whose length and starting position are indicated by second and third values in a control register) from one set of registers into an identified location (identified by a first value in the control register) in another set of registers.

Processing device for handling misaligned data

For certain applications, parts of the application data held in memory of a processing device (e.g. that are produced as a result of operations performed by the execution unit) are arranged in regular repeating patterns in the memory, and therefore, the execution unit may set up a suitable striding pattern for use by a send engine. The send engine accesses the memory at locations in accordance with the configured striding pattern so as to access a plurality of items of data that are arranged together in a regular pattern. In a similar manner as done for sends, the execution may set up a striding pattern for use by a receive engine. The receive engine, upon receiving a plurality of items of data, causes those items of data to be stored at locations in the memory, as determined in accordance with the configured striding pattern.

Processing device using variable stride pattern

A method and apparatus for handling overflow conditions resulting from arithmetic operations involving floating point numbers. An indication is stored as part of a thread's context indicating one of two possible modes for handling overflow conditions. In a first mode, a result of an arithmetic operation is set to the limit representable in the floating point format. In a second mode, a result of an arithmetic operation is set to a NaN.

Multiple modes for handling overflow conditions resulting from arithmetic operations

An apparatus, method and program for processing a signal received over a wireless channel. The apparatus comprises: a channel searcher configured to determine a profile of the channel in the form of energy values for a plurality of rays at respective channel positions, and an equalizer for equalizing the signal based on a variable window of the equalizer. The channel searcher is configured to estimate dispersion of the channel by determining a measure of variance of ray distance from a reference position within the channel profile weighted by ray energy. The equalizer is coupled to the channel searcher and arranged to adapt the window in dependence on the measure of energy-weighted ray distance variance.

Equalisation of a signal received over a wireless channel

A processor including: a first and at least a second data processing channel with enable logic for selectively enabling the second channel; logic for generating first and second storage addresses having a variable offset therebetween based on the same one or more address operands of the same storage access instruction; and circuitry for transferring data between the first address and a register of the first data processing channel and between the second address and a corresponding register of the second channel based on a same one or more register specifier operands of the access instruction. The first data processing channel performs an operation using one or more registers of the first data processing channel, and on condition of being enabled the second channel performs the same operation using a corresponding one or more of its own registers based on the same one or more operands of the data processing instruction.

Vector instruction execution to load vector data in registers of plural vector units using offset addressing logic

Disclosed herein are methods of processing transmissions in a wireless communication system to detect whether a transmission unit contains transmitted data, systems for processing transmissions in a digital communications system to detect the same, receivers for processing transmissions in a wireless communications system and computer readable media implementing a method for processing the same. In one embodiment, a method of processing transmissions in a wireless communication system to detect whether a transmission unit contains transmitted data includes: generating an averaged function of bit reliability indicators from a plurality of received samples and applying a test to compare an average of ln cosh(&#xb7;) (natural logarithm of the hyperbolic cosine) values for the reliability indicators, with a factor proportional to an average signal-to-disturbance ratio of the plurality of samples to determine if the transmission unit contains transmitted data.

Processing transmissions in a wireless communication system

A system and method for processing digital samples from a signal received via a wireless transmission channel in a wireless communications system. The method comprises: comparing a target signal quality value with an estimated received signal quality value; detecting if the estimated received signal quality value exceeds the target signal quality value for a period; and selecting one of a plurality of processing routines of differing sensitivities for processing the digital samples.

Processing digital samples in a wireless receiver

A method of power control in a wireless communication system wherein blocks are transmitted from a transmitter to a receiver on multiple wireless transport channels. The method comprises comparing a target signal quality value with a received signal quality value and providing the results of the comparing step to the transmitter to adjust transmit power based on the comparing step. A corresponding receiver is also provided.

Power control in a wireless communication system

A method of power control in a wireless communication system, wherein blocks are transmitted from a transmitter to a receiver via a wireless transport channel. The method comprises comparing a target signal quality value with a received signal quality value and providing the results of the comparing step to the transmitter to adjust transmit power based on the comparing step. The target signal quality value is set by the following steps: determining an initial target value; detecting if a data block has been received; detecting if received blocks have been successfully decoded; and decreasing the target value when pass blocks are received and increasing the target value when failed blocks are received subject to monitoring a period of inactivity on the transport channel in which no blocks are received.

A method of power control in a wireless communications system wherein blocks are transmitted from a transmitter to a receiver via a wireless transmission channel. The method comprises comparing a target signal quality value with a received signal quality value and providing the results of the comparing step to the transmitter to adjust transmit power based on the comparing step. The target signal quality value is set by the following steps: determining an initial target value; determining if received blocks have been successfully decoded; identifying the received blocks as pass or fail blocks; when pass blocks are received, comparing the target signal quality value with the received signal quality value and decreasing the target value only if the target value is greater than the received signal quality value less a margin.

A method of processing a signal in a wireless digital communications system, wherein a source of disturbance affects differently at least first and second portions of a received signal carrying user data and/or control data, the method comprising: identifying the second portion of the received signal, most affected by the source of disturbance; generating a first estimate of the disturbance (P) for received samples in the first, less affected portion of the received signal; generating a second estimate of the disturbance (P) for received samples in the second portion of the received signal; and using the first and second disturbance estimates to generate reliability information for the data bits corresponding to the received signal samples, for use in a decoding process to estimate the transmitted data bits.

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Bristol, United Kingdom

Edward Andrews