Intel Corporation

Motorola Corporation

Edward A Zarbock

Johanna M Swan

John Stephen Guzek

Ravi Kiran Nalla

Sabina J Houle

Mohit Mamodia

Drew W Delaney

Suresh V Pothukuchi

Robert L Sankman

Qing Ma

Debendra Mallik

Daoqiang Lu

Jiangqi He

Daewoong Suh

Javier Soto Gonzalez

Christopher L Rumer

Charles A Gealer

Jiamiao Tang

David W Jacobs

Charles A Rowell

Min Tao

Gloria Alejandra Camacho Bragado

Ming Lei

Javier Solo Gonzalez

A photonic package includes a photonic device having a photon emitter on the front side of the die. A beam of photons from the photon emitter passing from the front side to the backside of the die, passes through the substrate material of the die which is substantially transparent to the beam of photons, to the backside of the die. Other embodiments are also described.

Photonic package architecture

An apparatus includes a coreless substrate with a through-silicon via (TSV) embedded die that is integral to the coreless substrate. The apparatus includes a subsequent die that is coupled to the TSV die and that is disposed above the coreless substrate.

Die-stacking using through-silicon vias on bumpless build-up layer substrates including embedded-dice, and processes of forming same

Integration of sensor chips with integrated circuit (IC) chips. At least a first sensor chip including a first sensor is affixed to a first side of an interposer to hermitically seal the first sensor within a first cavity. An IC chip is affixed to a second side of the interposer opposite the first sensor, the IC chip is electrically coupled to the first sensor by a through via in the interposer. In embodiments, the first sensor includes a MEMS device and the IC chip comprises a circuit to amplify a signal from the MEMS device. The interposer may be made of glass, with the first sensor chip and the IC chip flip-chip bonded to the interposer by compression or solder. Lateral interconnect traces provide I/O between the devices on the interposer and/or a PCB upon which the interpose is affixed.

Interposer for hermetic sealing of sensor chips and for their integration with integrated circuit chips

Electronic devices and methods for fabricating electronic devices are described. One method includes attaching an optically transparent solid material to a body of semiconducting material in which microelectronic devices are formed. The method also includes attaching a first surface of a body portion, comprising a portion of the body, to a substrate while a portion of the optically transparent solid material is attached to a second surface of the body portion. The method also includes removing the optically transparent solid material from the second surface of the body portion after the attaching the first surface of the body portion to the substrate.

Using an optically transparent solid material as a support structure for attachment of a semiconductor material to a substrate

A method of forming a microelectronic package is provided. The method includes providing a silicon substrate having a plurality of carbon nanotubes disposed on a silicon layer and coupling the silicon substrate to a top surface of a packaging substrate, wherein the plurality of carbon nanotubes are coupled to a plurality of substrate pads of the packaging substrate. The method also includes removing the silicon substrate from the packaging substrate and disposing a die adjacent to the top surface of the packaging substrate, wherein the plurality of carbon nanotubes are coupled to a plurality of bump pads of the die.

Microelectronic package with carbon nanotubes interconnect and method of making same

A combined thermal interface material and second layer interconnect reflow material and method are disclosed.

Thermal interface material for combined reflow

A method for attaching an integrated circuit chip to a package substrate includes placing the integrated circuit onto the package substrate, and performing reflow to attach the integrated circuit to the package substrate. The temperature of the integrated circuit and package assembly is maintained at or above a predetermined temperature prior to dispensing an underfill between the package substrate and the integrated circuit. An underfill material is dispensed between the package substrate and the integrated circuit. The underfill material is cured to a first level of curing in the integrated circuit and package assembly. The underfill material is cooled in the integrated circuit and package assembly, and the underfill material is cured to a second level of curing in which the second level of curing is greater than the first level of curing.

Linked chip attach and underfill

A chip-to-chip optical interconnect includes a substrate, an optoelectronic die, and a waveguide structure. The substrate includes an optical via passing through the substrate. The optoelectronic die is disposed on the substrate and aligned to optically communicate through the optical via. A waveguide structure is positioned proximate to the substrate and aligned with the optical via to communicate optical signals with the optoelectronic die through the optical via.

Chip-to-chip optical interconnect

A microelectronic package including a microelectronic die having through silicon vias extending through a back surface thereof, which allows both an active surface and the back surface of the microelectronic die to have power, ground, and/or input/output signals connected to a flexible substrate. The flexible substrate may further connected to an external substrate through at least one external contact.

Through silicon via, folded flex microelectronic package

A method of marking glass includes providing a glass material with a surface ( ) and using a wire ( ) to mark the surface. The wire is softer than the glass material and does not damage the surface of the glass material.

Growing community of inventors

Gilbert, AZ, United States of America

Edward A Zarbock