Altera Corporation

Pts Corporation

Bops, Incorporated

Other

Billions of Operations Per Second

Edward A Wolff

Gerald George Pechanek

Patrick Rene Marchand

Edwin Franklin Barry

Grayson Morris

Edwin Frank Barry

David Carl Strube

Nikos P Pitsianis

Dale Edward Schneider

Carl Donald Busboom

Charles W Kurak, Jr

Ricardo E Rodriguez

Marco Jacobs

Thomas L Drabenstott

Marco C Jacobs

David Cureton Baker

Bryan Garnett Cope

Ayman Yehia Elezabi

Peter R Molnar

Details of a highly cost effective and efficient implementation of a manifold array (ManArray) architecture and instruction syntax for use therewith are described herein. Various aspects of this approach include the regularity of the syntax, the relative ease with which the instruction set can be represented in database form, the ready ability with which tools can be created, the ready generation of self-checking codes and parameterized test cases. Parameterizations can be fairly easily mapped and system maintenance is significantly simplified.

System core for transferring data between an external device and memory

A variety of advantageous mechanisms for improved data transfer control within a data processing system are described. A DMA controller is described which is implemented as a multiprocessing transfer engine supporting multiple transfer controllers which may work independently or in cooperation to carry out data transfers, with each transfer controller acting as an autonomous processor, fetching and dispatching DMA instructions to multiple execution units. In particular, mechanisms for initiating and controlling the sequence of data transfers are provided, as are processes for autonomously fetching DMA instructions which are decoded sequentially but executed in parallel. Dual transfer execution units within each transfer controller, together with independent transfer counters, are employed to allow decoupling of source and destination address generation and to allow multiple transfer instructions in one transfer execution unit to operate in parallel with a single transfer instruction in the other transfer unit. Improved flow control of data between a source and destination is provided through the use of special semaphore operations, signals and message synchronization which may be invoked explicitly using SIGNAL and WAIT type instructions or implicitly through the use of special 'event-action' registers. Transfer controllers are also described which can cooperate to perform 'DMA-to-DMA' transfers. Message-level synchronization can be used by transfer controllers to synchronize with each other.

Methods and apparatus for providing data transfer control

A scalable reconfigurable register file (SRRF) containing multiple register files, read and write multiplexer complexes, and a control unit operating in response to instructions is described. Multiple address configurations of the register files are supported by each instruction and different configurations are operable simultaneously during a single instruction execution. For example, with separate files of the size 32&#xd7;32 supported configurations of 128&#xd7;32 bit s, 64&#xd7;64 bit s and 32&#xd7;128 bit s can be in operation each cycle. Single width, double width, quad width operands are optimally supported without increasing the register file size and without increasing the number of register file read or write ports.

Methods and apparatus for dynamic instruction controlled reconfigurable register file

Low power architecture features and techniques are provided in a scalable array indirect VLIW processor. These features and techniques include power control of a reconfigurable register file, conditional power control of multi-cycle operations and indirect VLIW utilization, and power control of VLIW-based vector processing using the ManArray register file indexing mechanism. These techniques are applicable to all processing elements (PEs) and the array controller sequence processor (SP) to provide substantial power savings.

Methods and apparatus for power control in a scalable array of processor elements

Techniques for performing a bit rake instruction in a programmable processor. The bit rake instruction extracts an arbitrary pattern of bits from a source register, based on a mask provided in another register, and packs and right justifies the bits into a target register. The bit rake instruction allows any set of bits from the source register to be packed together.

Methods and apparatus for extracting bits of a source register based on a mask and right justifying the bits into a target register

Techniques for adding more complex instructions and their attendant multi-cycle execution units with a single instruction multiple data stream (SIMD) very long instruction word (VLIW) processing framework are described. In one aspect, an initiation mechanism also acts as a resynchronization mechanism to read the results of multi-cycle execution. This multi-purpose mechanism operates with a short instruction word (SIW) issue of the multi-cycle instruction, in a sequence processor (SP) alone, with a VLIW, and across all processing elements (PEs) individually or as an array of PEs. A number of advantageous floating point instructions are also described.

Methods and apparatus for initiating and resynchronizing multi-cycle SIMD instructions

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Stockton, CA, United States of America

Edward A Wolff