Hewlett-packard Development Company, L.p.

Edward A Cross

Bradley Dean Winick

Daniel V Zilavy

Robert B Smith

Michael S Allison

David R Maciorowski

Michael John Erickson

J Michael Andrewartha

Gerald J Kaufman, Jr

Christopher Shawn Kroeger

James Mankovich

James A Hess

John W Hover

Phillip David Langley

Systems, methodologies, media, computing devices, network adapters, and other embodiments associated with network communications are described. One exemplary system embodiment includes a multi-drop Ethernet network.

Multi-drop ethernet

A method for use in a computer system includes a first revision compatibility descriptor identifying a first plurality of compatible combinations of field-programmable unit codes. The method includes steps of: (A) determining whether the first revision compatibility descriptor identifies first field-programmable unit code for use in a first field-programmable unit as being compatible with the computer system; and (B) if the first revision compatibility descriptor does not identify the first field-programmable unit code as being compatible with the computer system, performing a step of updating the first revision compatibility descriptor to identify the first field-programmable unit code as being compatible with the computer system.

Field-replaceable unit revision compatibility

One embodiment of a non-volatile memory system comprises block-accessible non-volatile memory, random access memory arranged to be linearly addressable by a processor as part of the processor's memory address space, to be read from and written to by the processor, and logic interposed between the block-accessible non-volatile memory and the random access memory and arranged to write parts of the content of the random access memory in blocks to blocks of the non-volatile, block-accessible memory. The logic is arranged to monitor processor writes to the random access memory, and to write blocks of the random access memory that differ from a most recent copy in the non-volatile, block-accessible memory to the non-volatile, block-accessible memory.

Non-volatile storage for backing up volatile storage

Systems and methods of sharing removable media storage (RMS) devices in multi-partitioned systems are disclosed. An exemplary method may include receiving requests from a plurality of partitions of a processor to map at least one shared RMS device for the multi-partitioned system. The method may also include scheduling the requests if the shared RMS device is unavailable. The method may also include automatically mapping the at least one shared RMS device to the partitions one at a time as the at least one shared RMS device becomes available.

Systems and methods of sharing removable media storage devices in multi-partitioned systems

Systems, methodologies, media, and other embodiments associated with power management are described. One exemplary system embodiment includes an uninterrupted power supply (UPS) manager logic configured to determine a power status of one or more UPS devices attached to one or more external peripheral devices. The UPS manager logic can be configured to notify an appropriate operating system of a power loss to a selected external device.

Power management system for UPS attached to external devices

A system and method for power management in a computer system having multiple power grids is disclosed. The system includes a service structure operable in conjunction with an operating system (OS) instance executed on the computer system. At least one uninterrupted power supply (UPS) and at least one alternative source of power provide power to the multiple power grids. Where an UPS sends a loss of power notification to the service structure, the service structure is operable to maintain power supply to the grids from an available alternative source of power.

System and method for power management in a computer system having multiple power grids

Techniques are provided for simultaneously addressing multiple devices on a data bus, such as by transmitting over a data bus a single message that is received and processed by multiple devices on the bus. Multiple devices may be simultaneously addressed using the standard bus architecture and protocol, without affecting the operation of other devices on the bus. In particular, a master device may address a first subset of the plurality of devices on the bus using a primary address shared by the first subset of the plurality of devices. The master device may address a second subset of the plurality of devices using a secondary address shared by the second subset of the plurality of devices. The second subset is a subset of the first subset. The master device may then transmit information over the bus to the second subset of the plurality of devices.

Method and apparatus for addressing multiple devices simultaneously over a data bus

Techniques are provided for simultaneously ascertaining the status of a plurality of devices coupled to a data bus. A master device transmits at least one status request message over the data bus to a plurality of slave devices. In response, the plurality of slave devices transmit to the master device a status indicator message including a plurality of status indicators indicating statuses of the plurality of slave devices. The master device receives the status indicator message and ascertains the status of at least some of the plurality of slave devices by examining the status indicators. The status request message and/or status indicator message may be a message defined according to a protocol associated with the data bus. The data bus may, for example, be a serial data bus such as an IC bus.

Method and apparatus for ascertaining the status of multiple devices simultaneously over a data bus

A system for providing notification, to the associated operating system, of removal and replacement of I/O devices during operation of a multiprocessor computer system running multiple operating systems. The system includes a plurality of cells, each containing multiple RISC processors, low-level I/O firmware, a local service processor, scratch RAM, external registers, a memory and I/O manager, and interfacing hardware. Each partition comprises one or more cells and runs its own operating system (OS). Each cell is connected to a peripheral backplane containing a plurality of peripheral I/O card slots via a switch on the system backplane, which also connects the cell to a supervisory processor, which sends card slot status information to the appropriate cell. Each I/O (typically PCI) card slot has an associated latch which provides an indication, to the supervisory processor, that a platform event has occurred. Platform events include inserting or removing an I/O (peripheral device interface) card to/from a card slot, and opening an access panel that provides access to the I/O cards.

System for detection and routing of platform events in a multi-cell computer

A method of updating programmable device configuration code stored in EEPROMs of a system is operable on complex systems having separate management and system processors. The method includes executing a sequence for updating programmable device configuration code on a management processor of the system including erasing the EEPROMs, writing at least one block of configuration code to the EEPROMs, and checking for errors after writing. The errors checked for include failure of a FIFO to empty. Upon detecting errors, the method includes automatically retrying writes. Embodiments of the method are operable on systems having multiple serial busses interconnecting EEPROMs to a common configuration logic, and on systems having multiple management processors each capable of accessing the common configuration logic.

Method for accessing scan chains and updating EEPROM-resident FPGA code through a system management processor and JTAG bus

A dual power source system includes a first power source and a second power source operably coupled with an electrical device, as well as a switching mechanism capable of selecting between the first and second power sources. An uninterruptible power supply (UPS) is place in line with one of the first and second power sources leading to the electrical device. Sense circuitry is capable of identifying a power failure condition in either the first or second power sources. A controller utilizes signals from the sense circuitry to selectively switch between the first and second power sources while configuring the UPS in a manner of providing for a plurality of operational states that accommodate the electrical device with operational power despite any combination of power failures in the first and second power sources.

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Fort Collins, CO, United States of America

Edward A Cross