North American Philips Corporation

North American Philips Corp, Signetics Division

Philips Electronics North America Corporation

North American Philips Corp., Signetics Div.

Edward A Burton

Thomas D Fletcher

Charles E Dike

Farrell Lynn Ostler

Jeffrey Alma West

Benny T Ma

An electronic device comprises a circuit that is provided with incrementally modifiable power consumption control means. By applying a program signal to this control means the balance between speed and power consumption is optimized. A PLA circuit considerably benefits from this architecture.

Electronic circuit with programmable gradual power consumption control

An electronic circuit comprises a programmable cell that comprises a cell input, an output, a programmable component, programming means for selectively changing a state of the component, and coupling means for providing a signal path from the cell input to the output dependent on the component's state. The programmable component, e.g., a fuse, is located outside the signal path. Capacitances that limit the speed of operation in the read mode are considerably lower than in the prior art.

Programmable cell with a programmable component outside the signal path

An integrated circuit device is provided with user-programmable power-down means for disabling a particular circuit in the device under control of a user-specified state of an input signal supplied to the device. In particular, for PLDs a power-down feature of this kind is simple to implement, requiring no additional I/O pins on the device, considerably reduces power consumption and renders the device more versatile than prior art devices.

Integrated circuit device with user-programmable conditional power-down

High speed and high drive BiCMOS buffers, inverters, and gates receiving synchronous differential inputs are provided having at least two npn bipolar transistors and at least one nMOS transistor. The first bipolar transistor has a base receiving a noninverting input, a collector coupled to the high voltage rail, and an emitter coupled to the circuit output. In several embodiments, the second bipolar transistor has its collector coupled to the emitter of the first bipolar transistor, its emitter coupled to ground, and its base coupled to the source of an nMOS transistor which is receiving the inverting input at its gate. In these embodiments, the output is taken from the emitter of the first bipolar transistor and the collector of the second bipolar transistor with the first bipolar transistor pulling up when the input is high, and the second bipolar transistor pulling down when the input is low. Also, in several of the embodiments, the first bipolar transistor is coupled to a pMOS device with the collector connected to the source, and the emitter connected to the drain. The gate of the pMOS device is coupled to the inverting input, sometimes via the emitter of another bipolar transistor having its base connected to the inverting input. The pMOS device acts to pull up the output voltage of the circuit from the voltage provided at the emitter of the first bipolar transistor to the voltage of the high voltage rail.

Differential input buffer-inverters and gates

In a driver circuit, high- and low-impedance drive means (26 and 28 respectively) operate in parallel to effect a desired output transition. Adaptive control means 32 respond to a threshold value of the output signal (VO) and turn off the low-impedance drive means in the course of the output transition. The low initial output impedance of the driver circuit effects rapid charging of a line capacitance CL, while toward the end of the output transition the higher output impedance of the driver circuit more closely matches the input impedance ZL of a load circuit. This higher impedance dampens ringing and thereby reduces induced supply line noise which is conventionally associated with high-speed driver circuits.

CMOS driver circuit having reduced switching noise

A circuit employable as a differential multiplexer (10, 310, or 610) or as a differential logic gate (110, 210, 250, 410, or 510) of either the OR/NOR or EXCLUSIVE OR/EXCLUSIVE NOR type contains four pass gates that operate on four circuit input signals and are controlled by two additional circuit input signals. Two of the pass gates drive a bipolar transistor serially coupled to a first FET driven from the other two pass gates. Likewise, the second pair of pass gates drive another bipolar transistor serially coupled to another FET driven from the first pair of pass gates. The bipolar transistors supply respective circuit output signals. The two FETs are of a first polarity. The circuit preferably includes a pair of FETs of a second polarity opposite to the first polarity. The second pair of FETs are arranged so as to provide output pull-up/pull-down assistance for the bipolar transistors.

Circuit suitable for differential multiplexers and logic gates utilizing

In a memory element comprising interconnected logic gates with field effect transistors metastable states are to be avoided. The device's immunity against staying in metastable states is considerably raised by coupling a supply terminal of each logic gate to a power supply voltage via a base-emitter path of a bipolar transistor that has its collector coupled to the logic gate's output.

Memory element with high metastability-immunity

A high-speed low-power-consumption two-input arbiter circuit comprises two input inverters, two inverters cross-coupled to form a latch and two additional inverters that drive a difference detector. The detector responds only to a voltage difference on its inputs that exceeds a specified value. In this way, signals are blocked from appearing at the outputs of the detector while the latch is in a metastable state. Additionally, an n-input arbiter circuit comprises (n-1)+(n-2)+ . . . +[n-(n-1)] two-input arbiter circuits and logic circuitry connected to the outputs of the two-input circuits for supplying a priority signal to one and only one at a time of n output terminals of the n-input circuit.

Arbiter circuits with metastable free outputs

A voltage translator containing a bipolar transistor (Q1), a rectifier (10), a resistor (R1), and a first clamp (12) converts an input voltage (V.sub.I) into one or more output voltages of restricted voltage swing. The first clamp clamps the emitter voltage of the transistor when it is turned on. In one version, the translator includes a second clamp (14) that clamps the collector voltage of the translator when it is turned off. The translator then provides an output voltage (V.sub.O) inverse to the input voltage. In another version, the first clamp is connected between a voltage supply (V.sub.EE) and the emitter of the transistor. Its collector is connected directly to another voltage supply (V.sub.CC) so that the translator only makes non-inverting translations.

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Lindon, UT, United States of America

Edward A Burton