Qorvo Us, Inc.

Triquint Semiconductor Corporation

Edward A Beam, Iii

Jinqiao Xie

Paul Saunier

Xing Gu

Ming-Yih Kao

Deep C Dumka

Cathy Lee

Gary Alan Evans

Hua Q Tserng

Andrew Arthur Ketterson

William H Davenport

Andy Turudic

Hua-Quen Tserng

David Michael Fanning

Walter Anthony Wohlmuth

Jose L Jiminez

Cathy C Lee

Antonio Lucero

Aaditya Mahajan

A layer of yttrium (Y) and aluminum nitride (AlN) is employed as a back-barrier to improve confinement of electrons within a channel layer of a high electron mobility transistor (HEMT). As HEMT dimensions are reduced and a channel length decreases, current control provided by a gate also decreases, and it becomes more difficult to 'pinch-off' current flow through the channel. A back-barrier layer on a back side of the channel layer improves confinement of electrons to improve pinch-off but does not cause a second 2DEG to be formed below the back-barrier layer. The YAlN layer can be lattice-matched to the channel layer to avoid lattice strain, and a thin layer of YAlN provides less thermal resistance than HEMTs made with thicker back-barrier materials. Due to its chemical nature, a YAlN layer can be used as an etch stop layer.

High electron mobility transistors (HEMTS) including a yttrium (Y) and aluminum nitride (AIN) (YAIN) alloy layer

A high electron mobility transistor (HEMT) device with epitaxial layers that provide an electron Hall mobility of 1080&#xb1;5% centimeters squared per volt-second (cm/V&#xb7;s) at room temperature for a charge density of 3.18&#xd7;10/cmand method of making the HEMT device is disclosed. The epitaxial layers include a channel layer made of gallium nitride (GaN), a first spacer layer made of aluminum nitride (AlN) that resides over the channel layer, a first spacer layer made of AlGaN that resides over the first spacer layer, and a first barrier layer made of ScAlGaN that resides over the second spacer layer. In at least one embodiment, a second barrier layer made of AlGaN is disposed over the first barrier layer.

High electron mobility transistor (HEMT) device

A high electron mobility transistor (HEMT) device with epitaxial layers that include a gallium nitride (GaN) layer and an aluminum (Al) based layer having an interface with the GaN layer is disclosed. The Al based layer includes Al and an alloying element that is selected from Group IIIB transition metals of the periodic table of elements. The epitaxial layers are disposed over the substrate. A gate contact, a drain contact, and a source contact are disposed on a surface of the epitaxial layers such that the source contact and the drain contact are spaced apart from the gate contact and each other. The alloying element relieves lattice stress between the GaN layer and the Al based layer while maintaining a high sheet charge density within the HEMT device.

A field-effect transistor having a transconductance (gm) that remains within 65% of a maximum gm value over at least 85% of a gate voltage range that transitions the field-effect transistor between an on-state that allows substantial current flow through the channel layer and an off-state that prevents substantial current flow through the channel layer is disclosed. The field-effect transistor includes a substrate and a channel layer having a proximal boundary relative to the substrate and a distal boundary relative to the substrate. The channel layer is disposed over the substrate and comprises a compound semiconductor material that includes at least one element having a concentration that is graded between the proximal boundary and the distal boundary.

Field-effect transistor

A precursor cell for a transistor having a foundation structure, a mask structure, and a gallium nitride (GaN) PN structure is provided. The mask structure is provided over the foundation structure to expose a first area of a top surface of the foundation structure. The GaN PN structure resides over the first area and at least a portion of the mask structure and has a continuous crystalline structure with no internal regrowth interfaces. The GaN PN structure comprises a drift region over the first area, a control region laterally adjacent the drift region, and a PN junction formed between the drift region and the control region. Since the drift region and the control region form the PN junction having no internal regrowth interfaces, the GaN PN structure has a continuous crystalline structure with reduced regrowth related defects at the interface of the drift region and the control region.

Continuous crystalline gallium nitride (GaN) PN structure with no internal regrowth interfaces

The present disclosure relates to a process of forming a semiconductor device with a high thermal conductivity substrate. According to an exemplary process, a semiconductor precursor including a substrate structure, a buffer structure over the substrate structure, and a channel structure over the buffer structure is provided. The channel structure has a first channel surface and a second channel surface, which is opposite the first channel surface, adjacent to the buffer structure, and has a first polarity. Next, a high thermal conductivity substrate with a thermal conductivity greater than 400 W/mK is formed over the first channel surface. A heat sink carrier is then provided over the high thermal conductivity substrate. Next, the substrate structure and the buffer structure are removed to provide a thermally enhanced semiconductor device with an exposed surface, which has the first polarity.

Semiconductor device with high thermal conductivity substrate and process for making the same

The present disclosure relates to a process of forming a high thermal conductivity substrate for an Aluminum/Gallium/Indium (III)-Nitride semiconductor device. According to an exemplary process, a semiconductor precursor including a substrate structure and a buffer structure is provided. The buffer structure is formed over the substrate structure and has a first buffer surface and a second buffer surface. Herein, the second buffer surface is adjacent to the substrate structure and the first buffer surface is opposite the second buffer surface. Next, a high thermal conductivity substrate with a thermal conductivity greater than 400 W/mK is formed over the first buffer surface. A heat sink carrier is then provided over the high thermal conductivity substrate. The substrate structure is then substantially removed to provide a thermally enhanced precursor for the III-Nitride semiconductor device.

A semiconductor device includes a substrate, a relaxation layer, a channel layer, a polarization compensation layer, and a barrier layer. The relaxation layer is over the substrate and configured to reduce a total strain of the semiconductor device. The channel layer is over the relaxation layer. The polarization compensation layer is between the relaxation layer and the channel layer and configured to reduce a polarization between the relaxation layer and the channel layer. The barrier layer is over the relaxation layer and configured to polarize a junction between the barrier layer and the channel layer to induce a two-dimensional electron gas in the channel layer.

Double heterojunction field effect transistor with polarization compensated layer

A high electron mobility transistor (HEMT) device with epitaxial layers that include a gallium nitride (GaN) layer co-doped with silicon (Si) and germanium Ge and a method of making the same is disclosed. The HEMT device includes a substrate with epitaxial layers over the substrate. An n-type gallium nitride (GaN) layer is disposed on an interface surface of the epitaxial layers, wherein the n-type GaN layer is co-doped with silicon (Si) and germanium (Ge) that provide a carrier concentration of at least 1&#xd7;10cmand a root mean square (RMS) surface roughness that is no greater than 2 nm for a contact surface of the n-type GaN layer that is interfaced with the interface surface of the epitaxial layers.

High electron mobility transistor (HEMT) device and method of making the same

Embodiments include high electron mobility transistors (HEMTs) comprising a substrate and a barrier layer including a doped component. The doped component may be a germanium doped layer or a germanium doped pulse. Other embodiments may include methods for fabricating such a HEMT.

Doped gallium nitride high-electron mobility transistor

Embodiments include but are not limited to semiconductor devices including a barrier layer, a gallium nitride channel layer having a Ga-face coupled with the barrier layer, and a thermoconductive layer having a thermal conductivity of at least 500 W/(m&#xb7;K) within 1000 nanometers of a Ga-face of the gallium nitride channel layer. The semiconductor device may be a high-electron-mobility transistor or a semiconductor wafer. Methods for making the same also are described.

Gallium nitride on high thermal conductivity material device and method

Embodiments include apparatuses and methods related to an HFET. In embodiments, one or all of the buffer layer, the back-barrier layer, or the barrier layer may be formed of a digital alloy. In embodiments, the digital alloy may include alternating layers of alloys of aluminum, gallium, and nitrogen. Other embodiments may be disclosed or claimed herein.

Digital alloy layer in a III-nitrade based heterojunction field effect transistor

Embodiments of the present disclosure describe apparatuses, methods, and systems of an integrated circuit (IC) device. The IC device may include a buffer layer disposed on a substrate, the buffer layer including gallium (Ga) and nitrogen (N) and a barrier layer disposed on the buffer layer, the barrier layer including aluminum (Al) and nitrogen (N). The IC device may further include a gate terminal and a gate dielectric layer disposed between the gate terminal and the barrier layer and/or between the gate terminal and the buffer layer. In various embodiments, the gate dielectric layer may include a fluoride- or chloride-based compound, such as calcium fluoride (CaF).

Group III-nitride-based transistor with gate dielectric including a fluoride -or chloride- based compound

Embodiments of the present disclosure describe apparatuses, methods, and systems of an integrated circuit (IC) device. The IC device may include a buffer layer disposed on a substrate, the buffer layer including gallium (Ga) and nitrogen (N), a barrier layer disposed on the buffer layer, the barrier layer including aluminum (Al) and nitrogen (N), a regrown structure disposed in and epitaxially coupled with the barrier layer, the regrown structure including nitrogen (N) and at least one of aluminum (Al) or gallium (Ga) and being epitaxially deposited at a temperature less than or equal to 600&#xb0; C., and a gate terminal disposed in the barrier layer, wherein the regrown structure is disposed between the gate terminal and the buffer layer. Other embodiments may be described and/or claimed.

Growing community of inventors

Plano, TX, United States of America

Edward A Beam, Iii