Infineon Technologies Ag

Edvin Paparisto

Thomas Kern

Jan Otterstedt

Mihail Jefremow

Wolf Allers

Christoph Deml

Leonardo Castro

Stephan Rogl

Thomas Nirschl

Ulrich Backhausen

Jens Rosenbusch

Thomas Liebermann

Christian Peters

Xiangting Bi

The disclosure relates to an electronic memory system, and more specifically, to a system to emulate an electrically erasable programmable read-only memory, and a method to emulate an electrically erasable programmable read-only memory. According to an embodiment of the disclosure, a system to emulate an electrically erasable programmable read-only memory is provided, the system including a first memory section and a second memory section, wherein the first memory section comprises a plurality of storage locations configured to store data partitioned into a plurality of data segments and wherein the second memory section is configured to store information mapping a physical address of a data segment stored in the first memory section to a logical address of the data segment.

System and method to emulate an electrically erasable programmable read-only memory

The invention relates to an electronic memory system, and more specifically, to a system for emulating an electrically erasable programmable read only memory in a non-volatile memory device, and a method of emulating an electrically erasable programmable read only memory in a non-volatile memory device. According to an embodiment, a system for emulating an electrically erasable programmable read only memory is provided, the system including a Flash memory, wherein the Flash memory is configurable into a first region and a second region, wherein the first region is adapted to store a first class of data and the second region is adapted to store a second, different class of data.

System and method for emulating an EEPROM in a non-volatile memory device

The invention relates to an electronic memory system, and more specifically, to a system for providing voltage supply protection in a memory device, and a method for providing voltage supply protection in a memory device. According to an embodiment, a system for providing voltage supply protection in a memory device is provided, the system including a memory array including a plurality of memory cells arranged in a plurality of groups of memory cells, and a plurality of current limiting elements, wherein each group of memory cells is associated with at least one current limiting element.

System and method for providing voltage supply protection in a memory device

Embodiments relate to systems and methods including a step of switching between two or more erase operations and/or two or more write operations for erasing of and/or writing to least one memory cell of a nonvolatile memory enabling to select a most suitable erase and/or write operation for a particular erase and/or write operation within the memory.

Method and system for switchable erase or write operations in nonvolatile memory

The disclosure relates to an electronic memory system, and more specifically, to a system for adaptive bit rate programming of a memory device, and a method for adaptive bit rate programming of a memory device. According to an embodiment, a system for adaptive bit rate programming of a memory device including a plurality of memory cells is provided, wherein the memory cells are configured to be electrically programmable by application of a current supplied by a current source, the system including selection devices for selecting memory cells for programming based on availability of current from the current source.

System and method for adaptive bit rate programming of a memory device

A memory device, including a non-volatile memory device, a method for operating a memory device, and an apparatus for use with a memory device is disclosed. In one embodiment, the memory device includes at least one evaluation circuit for amplifying a signal resulting from the reading of a memory cell, and a device for precharging an output of the evaluation circuit to a predetermined voltage level.

Memory device, method for operating a memory device, and apparatus for use with a memory device

An integrated circuit having a memory arrangement is disclosed. In one embodiment, the memory arrangement includes a plurality of memory cells, a delete line for deleting the memory cells, and a read line for reading out the memory cells. There are either provided separate lines as delete line and as read line, or the same line serves both as delete line and as read line. The memory cell arrangement includes at least one delete memory sector and at least one read memory section. The number of memory cells of at least one delete memory sector does not concur with the number of memory cells of at least one read memory sector.

Integrated circuit having a memory arrangement

A method for reading out a memory cell, and a device to be used for reading out a memory cell. In one embodiment, the device includes a first circuit and a second circuit for regulating a voltage present at a line that is adapted to be connected with the memory cell to a predetermined value, wherein said first circuit includes a switching element, and wherein said first circuit is configured such that said switching element is switched on during a first regulating phase and is switched off during a second regulating phase.

Device for reading out a memory cell including a regulating circuit with parallel switching elements, and method

The invention relates to a procedure and a device for measuring memory cell currents, in particular for non-volatile memory components, where the device has a current mirroring device for mirroring a current flowing through a memory cell when it is being read, and delivering an analog current signal generated during the mirroring, or an analog current signal derived from it, to an analog output pad of a memory component.

Device and procedure for measuring memory cell currents

Precharge arrangement for read access for integrated nonvolatile memories having at least one memory cell (), at least one source line (), at least one bit line (), at least one sense amplifier () and at least one precharge potential, the bit line () continuously having the precharge potential in a deselected state of the bit line (), and the source line () having a predetermined reference potential, in particular a ground potential (), in a selected state of the bit line ().

Growing community of inventors

Munich, Germany

Edvin Paparisto