Saifun Semiconductors Ltd.

Spansion Israel Ltd

Cypress Semiconductor Corporation

Infineon Technologies Flash Ltd.

Other

Sajfun Semiconductors Ltd.

Saifum Semiconductors Ltd.

Eduardo Maayan

Boaz Eitan

Joseph Shor

Yoram Betser

Yair Sofer

Zeev Cohen

Ron Eliyahu

Ilan Bloom

Ran Dvir

Ameet Lann

Guy Cohen

Alexander Kushnarenko

Oleg Dadashev

Eli Lusky

Yan Polansky

David Finzi

Shai Eisen

Shahar Atir

Disclosed is a non-volatile memory (NVM) device including an array of NVM cells segmented into at least a first sector and a second sector and at least one sensing circuit to sense a state of a target NVM cell in the first sector using a reference current of the second sector received from at least a dynamic reference cell.

Methods, circuits, devices, and systems for sensing an NVM cell

Methods, circuits, devices and systems for sensing an NVM cell

A method includes minimizing current leaking through a virtual ground pipe during access of NROM memory cells. The minimizing includes operating two neighboring memory cells generally together, which includes connecting an operation voltage to a shared local bit line of the two neighboring memory cells and connecting the external local bit lines of two neighboring memory cells to a receiving unit, such as a ground supply or two sense amplifiers. Also included is an array performing the method.

NROM device with reduced power unit

Device to program adjacent storage cells of different NROM cells

The present invention includes methods, circuits and systems for reading non-volatile memory ('NVM') cells, including multi-level NVM cells. According to some embodiments of the present invention, there may be provided a NVM cell threshold voltage detection circuit adapted to detect an approximate threshold voltage associated with a charge storage region of a NVM cell, where the NVM cell may be a single or a multi-charge storage region cell. A decoder circuit may be adapted to decode and/or indicate the logical state of a NVM cell charge storage region by mapping or converting a detected approximate threshold voltage of the charge storage region into a logical state value.

Methods, circuits and systems for reading non-volatile memory cells

A method for reading a bit of a memory cell in a non-volatile memory (NVM) cell array, the method comprising providing a memory cell comprising a bit to be read and at least one other bit not to be read, and reading the bit to be read with respect to a multi-bit reference cell, the reference cell comprising a first bit at a first non-ground programmed state and a second bit at a second non-ground programmed state. Compared with the prior art, the present invention may enable achieving an improved sensing accuracy together with improved read disturb immunity.

Reading array cell with matched reference cell

Disclosed is a method of reducing the neighbor effect while reading data in a non-volatile memory array. The method includes sensing adjacent memory cells. The sensing of the two adjacent cells is performed substantially simultaneously and through at least a partially shared sensing path.

Method for reading a memory array with neighbor effect cancellation

A die for a memory array may store Flash and EEPROM bits in at least one Nitride Read Only Memory (NROM) array. Each array may store Flash, EEPROM or both types of bits.

Multiple use memory chip

A method for programming one or more reference cells is described. The reference cell is programmed a predetermined amount, its program state is sensed relative to a prescribed cell on the same die (e.g., a memory cell or a golden bit cell), and the programming process continues until the reference cell fails a preselected read operation. In one preferred embodiment, the memory cell used during the reference cell programming process is the cell in the memory array having the highest native threshold value. In another preferred embodiment, the memory cell used during the reference cell programming process is a native cell that is on-board the die containing the memory array, but not a cell within the memory array.

Method for programming a reference cell

Methods for minimizing current consumption in a memory array during programming of non-volatile memory cells, such as NROM cells, in the array include: programming a cell without having a direct current flowing from a positive supply to ground through the array, programming a plurality of cells with programming pulses without discharging a global bit line carrying a programming voltage between programming pulses, and programming a cell with transient currents.

Reduced power programming of non-volatile cells

A non-volatile device and method of operating the device including changing a read reference level for reading a group of memory cells as a function of changes in a threshold voltage distribution of a different group of memory cells. The changing step may include determining a history read reference level of a history cell associated with a group of memory cells of a non-volatile memory cell array and comparing sensed logical state distributions with stored logical state distributions.

Non-volatile memory device and method for reading cells

A method for sensing a signal received from an array cell within a memory array, the method comprising the steps of generating an analog voltage Vddr proportional to a current of a selected array cell of the memory array, and comparing the analog voltage Vddr with a reference analog voltage Vcomp to generate an output digital signal. A method is also provided for sensing a memory cell by transforming a signal from a memory cell to a time delay, and sensing the memory cell by comparing the time delay to a time delay of a reference cell. Related apparatus is also disclosed.

Apparatus and methods for multi-level sensing in a memory array

A method for operating an electrically erasable programmable read only memory (EEPROM) array includes providing an array including a multiplicity of memory cells, wherein each memory cell is connected to a word line and to two bit lines, selecting one of the memory cells, and erasing a bit of the selected memory cell while applying an inhibit word line voltage to a gate of an unselected memory cell. An EEPROM array is also described, the array including a multiplicity of NROM memory cells, wherein each memory cell is connected to a word line and to two bit lines, and wherein each NROM cell is individually erasable and individually programmable without significantly disturbing unselected cells.

Growing community of inventors

Kfar Saba, Israel

Eduardo Maayan