Raytheon Company

Raytheon Bbn Technologies Corp.

Eduardo M Chumbes

Thomas E Kazior

Kelly P Ip

Jeffrey R LaRoche

Mohammad Soltani

Brian D Schultz

William E Hoke

Shahed Reza

Jason C Soric

Adam E Peczalski

Kevin Iliff McCarthy

John P Bettencourt

Gerhard Sollner

Kamal Tabatabaie

Jeffrey H Saunders

John Logan

Jeffrey Laroche

Michael S Davis

Abbas Torabi

Dale M Shaw

Mohammad Soitani

Steven K Brierley

Brian T Appleton, Jr

Kevin Mccarthy

A semiconductor device having a substrate and an orthorhombic polar crystalline oxide k-AlOlayer epitaxially and heterogeneously integrated above a wurtzite single-crystal Group III-Nitride layer comprising AlN disposed above the substrate.

AIN channel heterostructure field effect transistor

A strain compensated heterostructure comprising a substrate comprising silicon carbide material; a first epitaxial layer comprising single-crystal aluminum nitride material formed on a top surface of the substrate; a second epitaxial layer formed on the first epitaxial layer opposite the top surface of the substrate, the second epitaxial layer comprising single-crystal scandium aluminum nitride material; and a third epitaxial layer formed on the second epitaxial layer opposite the first epitaxial layer, the third layer comprising single-crystal aluminum nitride material.

Strain compensated rare earth group III-nitride heterostructures

A field effect transistor having a field plate structure for shaping an electric field in a region between the gate and the drain, such field plate structure having: a dielectric layer disposed on gate and on the surface of the semiconductor in the region between gate and the drain; and electric charge disposed in portions of the dielectric layer, a portion of such charge being disposed in the dielectric layer over an upper surface of the gate and another portion of the change extending from the upper surface of the gate into the region between gate and the drain; and wherein the electric charge solely produces the electric field.

Field effect transistor having field plate

Embodiments of a single-chip ScAIN tunable filter bank include a plurality of switching elements, and a plurality of channel filters integrated on a monolithic platform. The monolithic platform may comprise a single crystal base and each of the switching elements may comprise at least one of a scandium aluminum nitride (ScAIN) or other Group III-Nitride transistor structure fabricated on the single crystal base. In these embodiments, each channel filter comprises a multi-layered ScAIN structure comprising one or more a single-crystal epitaxial ScAIN layers fabricated on the single crystal base. The ScAIN layers for each channel filter may be based on desired frequency characteristics of an associated one of the RF channels.

Tunable monolithic group III-nitride filter banks

A Group III-V semiconductor structure having a semiconductor device. The semiconductor device has a source and drain recess regions extending through a barrier layer and into a channel layer. A regrown, doped Group III-V ohmic contact layer is disposed on and in direct contact with the source and drain recess regions. A gate electrode is disposed in a gap in the regrown, doped Group III-V ohmic contact layer and on the barrier layer A dielectric structure is disposed over the ohmic contact layer and over the barrier layer and extending continuously from a region over the source recess region to one side of the stem portion and then extending continuously from an opposite side of the stem portion to a region over the drain recess region, a portion of the dielectric structure being in contact with the stem portion and the barrier layer.

Group III-V semiconductor structures having crystalline regrowth layers and methods for forming such structures

Photonic devices having a photonic waveguiding layer, and a cladding layer, disposed on the photonic waveguiding layer, and where the cladding section is a material comprising Scandium. The cladding layer may include a material comprising AlScN material where 0&#x3c;x&#x2264;0.45.

Photonic devices

Photonic devices having a quantum well structure that includes a Group III-N material, and a AlScN cladding layer disposed on the quantum well structure, where 0&#x3c;x&#x2264;0.45, the AlScN cladding layer having a lower refractive index than the index of refraction of the quantum well structure.

A Group III-Nitride quantum well laser including a distributed Bragg reflector (DBR). In some embodiments, the DBR includes Scandium. In some embodiments, the DBR includes AlScN, which may have 0&#x3c;x&#x2264;0.45.

A Group III-V semiconductor structure having a semiconductor device. The semiconductor device has a source and drain recess regions extending through a barrier layer and into a channel layer. A regrown, doped Group III-V ohmic contact layer is disposed on and in direct contact with the source and drain recess regions. A gate electrode is disposed in a gap in the regrown, doped Group III-V ohmic contact layer and on the barrier layer A dielectric structure is disposed over the ohmic contact layer and over the barrier layer and extending continuously from a region over the source recess region to one side of the stem to portion and then extending continuously from an opposite side of the stem portion to a region over the drain recess region, a portion of the dielectric structure being in contact with the stem portion and the barrier layer.

Photonic devices having AlScN and AlGaN materials, where Al is Aluminum, Sc is Scandium, Ga is Gallium, and N is Nitrogen and where 0&#x3c;x&#x2264;0.45 and 0&#x2264;y&#x2264;1.

A semiconductor structure having: a Group III-N semiconductor; a first dielectric disposed in direct contact with the Group III-N semiconductor; a second dielectric disposed over the first dielectric, the first dielectric having a higher dielectric constant than the second dielectric; a third dielectric layer disposed on the first dielectric layer, such third dielectric layer having sidewall abutting sides of the second dielectric layer; and a gate electrode contact structure. The gate electrode structure comprises: stem portion passing through, and in contact with, the first dielectric and the second dielectric having bottom in contact with the Group III-V semiconductor; and, an upper, horizontal portion extending beyond the stem portion and abutting sides of the third dielectric layer. An electrical interconnect structure has side portions passing through and in contact with the third dielectric layer and has a bottom portion in contact with the horizontal portion of the gate electrode contact structure.

Nitride structures having low capacitance gate contacts integrated with copper damascene structures

Photonic and electric devices on a common layer

A semiconductor structure having a buffer layer, a pseudomorphic, impurity doped, back-barrier layer disposed on the buffer layer, a channel layer disposed on the back-barrier layer, the channel layer lattice matched to the buffer layer, and a top barrier layer disposed on the channel layer. A Group III-Nitride transition layer is disposed between the buffer layer and the pseudomorphic back-barrier layer. The buffer layer and the pseudomorphic back-barrier layer are both Group III-Nitride materials. The Group III-Nitride material of the buffer layer is different from the Group III-Nitride material in the back-barrier layer. The back-barrier layer has a wider bandgap of than the buffer layer bandgap. The composition of the Group III-Nitride material in the transition layer varies from the composition of the Group III-Nitride material in the buffer layer to the composition of the Group III-Nitride material in the pseudomorphic back-barrier layer as a function of distance from the buffer layer.

Group III&#x2014;nitride double-heterojunction field effect transistor

A semiconductor structure having a Group III-N semiconductor layer disposed on a substrate. A multi-layer, electrical contact structure in contact with the Group III-N semiconductor layer includes a gold-free contact layer in contact with the Group III-N semiconductor layer; and a gold-free electrically conductive etch stop layer electrically connected to the gold-free contact layer. An electrically conductive via passes through the substrate to the etch stop layer. The structure includes a plurality of electrode structures, each one providing a corresponding one of a source electrode structure, drain electrode structure and a gate electrode structure. The source electrode structure, drain electrode structure and gate electrode structure include: an electrical contact structure and an electrode contact. The electrode contacts have the same gold-free structure and have co-planar upper surfaces.

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Andover, MA, United States of America

Eduardo M Chumbes