Arm Limited

Eduard Vardanyan

Sean James Salisbury

Chiranjeev Acharya

Arthur Brian Laughton

Premkishore Shivakumar

Jaume Cabecerans Betran

Resizing circuitry comprises at least one buffer having buffer entries each corresponding to one of at least two shift registers, each shift register comprising storage circuits connected in a ring to transfer a token bit between storage circuits. Selection circuitry controls, based on the shift registers, writing of data sections of input data units having a first number of data sections to the buffer(s), to form output data units having a second number of data sections. For a given buffer entry corresponding to a given shift register, depending on whether the token bit is stored in a first or second subset of storage circuits, the selection circuitry controls writing of a selected data section of a received input data unit to the given buffer entry or prevents overwriting of the given buffer entry. At least two of the shift registers have different relative arrangements of the first and second subsets of storage circuits.

Resizing circuitry

An on-chip interconnect comprises control circuitry which responds to a burst read request received at an initiating requester interface, to control issuing of at least one read request to at least one target completer device via at least one target completer interface. For a chunking enabled burst read transaction, the control circuitry supports returning the requested data items to the initiating requester device in a number of data transfers, with an order of the data items in the data transfers permitted to differ from a default order and each data transfer specifying chunk identifying information identifying which portion of the data items is represented by returned data for that data transfer. For a data transfer returned to the initiating requester device based on data returned from one of a second subset of completer interfaces, the control circuitry generates the chunk identifying information to be specified by the given data transfer.

Chunking for burst read transactions

Routing circuitryis provided for routing transaction requests to a selected destination node. The routing circuitry supports read requests requiring a read response, write requests requiring a write response and at least one type of atomic data access request requiring both a read response and a write response. Request regulatorsare provided to monitor resource usage for read, atomic and write requests, and issue circuitrycontrols the issuing of a transaction request received from a requesting node, in dependence on resource usage monitoring performed by the request regulators. The issue circuitry controls the issuing of atomic requests in dependence on the resource usage monitored by the write request regulator and the resource usage monitored by the atomic request regulator.

Regulation for atomic data access requests

Data access routing circuitryis provided for routing data access request to a selected destination node. The data access routing circuitry supports read requests requiring a read response, write requests requiring a write response and at least one type of atomic data access request requiring both a read response and a write response. Resource allocation circuitryis provided to control allocation of resource for handling data access requests which require a read response. The resource allocation circuitryreserves resource for handling the at least one type of atomic data access request and prevents use of the reserved resourcefor handling read requests.

Resource allocation for atomic data access requests

Processing circuitryincludes data storage circuitryfor storing one or more ordered sets of data entries. Access control circuitrycontrols access during a given access cycle to a given ordered set of data entries in dependence upon, for that given set of data entries, a head-entry flag, a next-following-entry flag and preceding-cycle data. The head-entry flag indicates the oldest data entry for the given ordered set, the next-following-entry flag indicates the next oldest entry and the preceding-cycle flag indicates whether the given ordered set was accessed during a preceding access cycle. If the given ordered set was accessed during the preceding access cycle, then the next-following entry corresponding to the next-following flag is accessed during the current access cycle instead of that indicated by the head flag.

Accessing ordered sets of data entries

An interconnect for providing data access between nodes of an integrated circuit, comprises a predetermined type of ingress port comprising routing circuitry responsive to a read-triggering request received from a requesting node to select from a selected egress port via which signals are to be routed to a destination node to control the destination node to return at least one read response dependent on data read from a target storage location. In response to the read-triggering request, the routing circuitry obtains a relative data width indication specifying whether read responses received at the selected egress port have a narrower data width than read responses to be provided to the requesting node by the predetermined type of ingress port, and controls allocation of resource for handling the read-triggering request or the at least one read response depending on the relative data width indication.

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Sheffield, United Kingdom

Eduard Vardanyan