Synopsys, Inc.

Eduard Rudolf Cerny

Dmitry Korchemny

Pei-Hsin Ho

Kevin Michael Harer

Ashvin Mark Dsouza

Ilya Kudryavtsev

Yogesh Pandey

Surrendra A Dudani

Saptarshi Ghosh

Kaushik De

Bhaskar Pal

Pallab Dasgupta

Partha Pratim Chakrabarti

Dmitriy Mosheyev

Hanish Singla

Diganchal Chakraborty

Samik Sengupta

Sivaprasad Acharya

Ashok Kumar Bhatt

Gerald Taylor

William R Dufresne

The present disclosure generally relates to an analog mixed-signal (AMS) design verification system. In particular, the present disclosure relates to a system and method for system verification. One example method includes: obtaining an electronic representation of the circuit design; generating at least a portion of a waveform using the electronic representation of the circuit to obtain a first segment of the waveform associated with the circuit; converting, via the one or more processors, one or more measurement functions to code for performing the one or more computations on the first segment of the waveform; performing one or more computations on the first segment of the waveform using the code; and identifying when a behavior of the circuit violates a design specification based on whether a result of the one or more computations meets a threshold.

On-the-fly computation of analog mixed-signal (AMS) measurements

A design for an analog mixed-signal (AMS) circuit is accessed. An assertion for verifying the behavior of an analog signal in the AMS circuit is also accessed. The assertion is expressed in an assertion language for AMS circuits. A processor verifies the assertion against the predicted behavior of the analog signal in the AMS circuit. In various embodiments, the assertion language contains predefined classes for assertions in the temporal domain, for assertions in the frequency domain, and for assertions based on functional dependencies of an output analog signal on an input analog signal.

Analog mixed-signal assertion-based checker system

Synthesis of functional coverage (e.g., covergroups) is optimized for hardware emulation. The optimization may reduce the number of logic gates used to implement the hardware emulator circuits or reduce the computer resources used to synthesize the hardware emulator circuits. The optimization may also prevent the synthesis of unnecessary circuits. In another aspect, the optimization may result in a representation that may be used both to synthesize hardware emulation circuits and as part of formal verification. This may result in a model that can be used for formal verification, hardware emulation, and software simulation.

Unified functional coverage and synthesis flow for formal verification and emulation

A method of verifying a circuit design, includes, in part, identifying a first groups of signals associated with the circuit, selecting a signal sampling window depth, performing a first verification of the circuit using a first test bench adapted to cause transitions in the first group of signals, storing values of the signals in the first group during each of the cycles defined by the sapling window depth to generate a first functional coverage, performing a second verification of the circuit design using a second test bench to generate a second functional coverage, comparing the second functional coverage to the first functional coverage, and automatically generating one or more cover property statements if the second functional coverage is less than the first functional coverage. The one or more cover property statements cause the second functional coverage to become equal to or greater than the first functional coverage.

Automatic definition and extraction of functional coverage metric for emulation-based verification

A system receive as input a circuit design and a description of the behavior of the circuit design specified as assertions. The system generates a model used for verifying that the circuit design satisfies the specified behavior. The system generates an alternating automaton representing the assertions. The alternating automaton may be non-deterministic. The system translates the alternating automaton to a finite state machine (FSM) that may be represented using a representation such as a register transfer level (RTL) representation. The system models existential transitions in the state machine using variables. As a result, the system generates fewer states in the state machine, thereby requiring significantly less memory resources for processing the assertion. The system validates the circuit design using the state machine for further design and manufacture of the circuit.

Efficient execution of alternating automaton representing a safety assertion for a circuit

Groups of signals in an electronic design for which interesting assertions, such as assert, assume and cover properties, can be generated are identified. A sliding temporal window of fixed depth is used to sample unique present and past value combinations of signals in the signals groups generated by one or more simulations or emulations. The values of signals in the signal groups are organized into truth tables. Minimal functional relations are extracted from the truth tables, using techniques similar to those for synthesis of partial finite memory machines from traces, and used to generate assertions. The assertions are filtered using a cost function and pertinence heuristics, and a formal verification tool used to prune unreachable properties and generate traces for reachable cover properties. Syntactically correct assert, assume and cover property statements for the generated properties are instantiated and packaged into a file suitable for further simulation or emulation or formal verification.

Assertion extraction from design and its signal traces

One embodiment of the present invention provides a system which verifies a circuit design by biasing input stimuli for the circuit design to satisfy one or more temporal coverage properties to be verified for the circuit design. This system performs a simulation in which random input stimuli are applied to the circuit design. The system performs the simulation by using a finite state automaton (FSA) instance for a temporal coverage property to observe inputs and outputs of the circuit, and by using soft constraints associated with the FSA instance to bias the input stimuli for the circuit design so that the simulation is likely to progress through a sequence of states which satisfy the temporal coverage property.

Constrained random simulation coverage closure guided by a cover property

Systems and techniques for evaluating assertions during circuit verification are described. During operation, m semantically equivalent assertions can be identified, wherein each of the m semantically equivalent assertions is evaluated using n logical expressions. Next, a set of vectors based on the m semantically equivalent assertions can be determined, wherein each vector element corresponds to a logical expression that is used for evaluating one of the m semantically equivalent assertions. The m semantically equivalent assertions can then be evaluated, in parallel, using the set of vectors.

Vector evaluation of assertions

One embodiment of the present invention provides systems and techniques to extract assume properties from a constrained random test-bench. During operation, the system can receive a constrained random test-bench for verifying the design-under-test (DUT), wherein the constrained random test-bench includes a statement which assigns a random value to a random variable according to a constraint. Next, the system can modify the constrained random test-bench by replacing the statement with another statement which assigns a free input variable's value to the random variable. The system can also add a statement to the constrained random test-bench that toggles a marker variable to localize the scope of the statement. The system can then generate an assume property which models the constraint on the free input variable. The assume property can then be used by a formal property verification tool to verify the DUT.

Method and apparatus for extracting assume properties from a constrained random test-bench

Relates to automatic conversion of assumption constraints, used in circuit design verification, that model an environment for testing a DUT/DUV, where the assumptions specify sequential behavior. Such assumptions are converted, with the use of logic synthesis tools, into a gate-level representation. For formal verification, a verification output is constructed from the gate-level representation and DUT/DUV assertion-monitoring circuitry. A formal verifier seeks to prove the verification output cannot indicate a design error. For simulation verification, the gate-level representation is converted into a hybrid representation comprising pipelines and combinational constraints. During simulation, the pipelines hold state information necessary for a solution, of the combinational constraints, to be in accord with the sequential assumption constraints. For certain sequential assumption constraints, the combinational constraints are insufficient to insure avoidance of deadend states. In a deadend state, an assumption is violated. A method is presented for augmenting the combinational constraints to avoid deadend states.

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Worcester, MA, United States of America

Eduard Rudolf Cerny