Synopsys, Inc.

Eduard Petrus Huijbregts

Solaiman Rahim

Qing Su

Pankaj Singla

Stephan Houben

Avijit Dey

A method includes acquiring timing analysis data associated with a cell and activity data of one or more inputs of the cell, determining a glitch toggle rate for an output of the cell based on the activity data of the one or more inputs of the cell and the timing analysis data, and estimating a glitch power based on at least the glitch toggle rate.

Enhanced glitch estimation in vectorless power analysis

A logically hierarchical netlist may be split along physical partition boundaries while retaining information on the logical hierarchy. Nets can be driven to higher levels of hierarchy in order to maintain connectivity and enable the original logical function. A mapping of nets can be created. During the design process merging of physical partitions may result in a new logically hierarchical netlist which retains the hierarchy of the original logically hierarchical netlist. The lowest common hierarchical ancestor (LCA) is identified and then the appropriate cells and nets are included during the merging process.

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Eindhoven, Netherlands

Eduard Petrus Huijbregts