U.S. Philips Corporation

Eduard M Van Der Ouderaa

Hendrik Vrielink

Adriaan Willemse

Signal processor device having a processor module and a conditional interrupt module for use in a multiprocessor system employing these signal processor devices. The processor module has address, data and control inputs and outputs, including an interrupt signal input for receiving an incoming interrupt request signal. The signal processor device has at least one conditional interrupt module in which the identity address of the signal processor is present, said interrupt module having inputs for receiving an incoming external interrupt request signal with corresponding destination address. The conditional interrupt module also has comparators in which its identity address is compared with the destination address. If the addresses agree, an interrupt signal is fed to the interrupt signal input of the processor module. The processor module may also have an interrupt signal output and be provided with an arbitration module to prevent conflicts between several interrupt requests. The provision of the conditional interrupt module enables interrupts to be processed in a multiprocessor system employing a plurality of such devices without all the devices being initially interrupted and without it being necessary to provide a multiplicity of interrupt lines.

Signal processor device with conditional interrupt module and

For mutual bidirectional communication, two active functional units are connected by a bidirectional data bus line and one unidirectional control line for each of the two directions. Both active functional units are each time connected, via an output circuit, to the relevant single connections of the data bus line. The output circuits have at least one first state in order to produce per first state, at a low impedance, a first data state on the connection, and one second state for generating, at a high impedance, a second data state for the connection. When such a first and a second data states are simultaneously present on one and the same connection, the former state dominates. The second state can thus also act as an inactive state. A bidirectional data transport cycle for the first active functional unit includes the following steps: supplying data--transmitting a request signal--detecting an acknowledge signal--deactivating the transmitted data--changing over to the receive state--terminating the receive state--transmitting the acknowledge signal.

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Eindhoven, Netherlands

Eduard M Van Der Ouderaa