U.S. Philips Corporation

Nxp B.v.

St-ericsson Sa

Koninklijke Philips Corporation N.v.

Pxp B.v.

Eduard Ferdinand Stikvoort

Mihai Adrian Tiberiu Sanduleanu

Mihai A T Sanduleanu

Eise Carel Dijkmans

Antonia Cornelia Van Rens

Gilles J Chevallier

Ram P Aditham

Rudy J Van De Plassche

Leonard J Esser

Alphons A M L Bruekers

Jozef Reinerus Maria Bergervoet

Arthur H Van Roermund

Eric H Persoon

Adrianus Sempel

Eric Antonius Maria Klumperink

Simon Minze Louwsma

Eddy A Odijk

Hermanus Josephus Wilting

Christian J Vandenbulcke

Gerardus C M Gielis

Peter J Naus

Adrianus W M Van Den Enden

Peter J Rutten

Petrus G M Baltus

Idrissa Cissé

Antoon M H Tombeur

The present invention relates to a polar modulation apparatus and method, in which a polar-modulated signal is generated based on separately processed phase modulation (PM) and amplitude modulation (AM) components of an input signal. An amplified polar modulated output signal is generated in accordance with the phase modulation and amplitude modulation components by using a differential power amplifier circuitry() and supplying an amplified phase modulation component to a differential input of the differential power amplifier circuitry(). A bias input of the differential power amplifier circuitry() is controlled based on the amplitude modulation component, so as to modulate a common-mode current of the differential power amplifier circuitry(). Thereby, a new concept of a polar modulator with static DC-DC converter and power and/or efficiency and/or linearity controlled output power amplifier can be achieved.

Polar modulation apparatus and method with common-mode control

The present invention relates to an oscillator circuit and a method of controlling the oscillation frequency of an in-phase signal and a quadrature signal. First oscillator means () with a first differential oscillator circuit and a first differential coupling circuit are provided for generating the quadrature signal. Furthermore, second oscillator means () with a second differential oscillator circuit and a second differential coupling circuit are provided for generating the in-phase signal. A frequency control means is provided for varying the oscillation frequency of the in-phase signal and the quadrature signal by controlling at least one of a common-mode current and a tail current of the first and second oscillator means. Thereby, a high-frequency IQ oscillator with high linearity is obtained.

Quadrature oscillator with high linearity

The present invention relates to a polar modulation apparatus and method, in which a polar-modulated signal is generated based on separately processed phase modulation (PM) and amplitude modulation (AM) components of an input signal. An amplified polar modulated output signal is generated in accordance with the phase modulation and amplitude modulation components by using a differential power amplifier circuitry and supplying an amplified phase modulation component to a differential input of the differential power amplifier circuitry. A bias input of the differential power amplifier circuitry is controlled based on the amplitude modulation component, so as to modulate a common-mode current of the differential power amplifier circuitry. Thereby, a new concept of a polar modulator with static DC-DC converter and power and/or efficiency and/or linearity controlled output power amplifier can be achieved.

A detector arrangement for detecting a frequency error between an input signal (DATA) and a reference signal. The detector arrangement comprising first latch circuitry (L, L) for sampling a quadrature component (CKQ) of the reference signal based on the input signal, to generate a first binary signal (PDQ); second latch circuitry (L, L) for sampling an in-phase component (CKI) of the reference signal based on the input signal, to-generate a second binary signal (PD I); third latch circuitry (L) for sampling the first binary signal based on the second binary signal, to generate the frequency error signal (FD). The detector further comprising control circuitry (TS) for selectively suppressing operation of a charge pump () to which the first binary signal (PDQ) is supplied, in response to a control signal derived from the second binary signal.

Fast phase-frequency detector arrangement

It is disclosed a combinatorial logic circuit comprising a first logic block (B) coupled to a supply terminal (V) via a first resistor means (RI) and via a second resistor means (R) for receiving respective first and second supply currents (). The circuit further comprises a second logic block (B) coupled to the supply terminal (V) via the first resistor means (R) and via the second resistor means (R) for receiving respective third and fourth supply currents (). A first output terminal (Q&#x2212;) coupled to the first block (B) and to the first resistor means (R). A second output terminal (Q+) coupled to the second logic block (B) and to the second resistor means (R). A first current source (I) coupled to at least one of the first output terminal (Q&#x2212;) and/or second output terminal (Q+) for providing a first supply current (I) through the first resistor means (R), which is substantially equal to a second supply current (I) through the second resistor means (R).

Combinatorial logic circuit

Devices () comprising feedback-less amplifiers () that are gain controlled introduce linear relationships between output signals and input signals of the feedback-less amplifiers () by providing the feedback-less amplifiers () sub-circuits in the form of first transistors () operated in their triode regions for receiving input signals and second sub-circuits in the form of second transistors () for receiving control signals and third sub-circuits in the form of resistors () for generating output signals, whereby the respective first and second and third sub-circuits form a serial path. Second circuits () receive gain signals and convert the gain signals into the control signals. The control signals are copies of the gain signals. The second circuits () comprise current sources () and third and fourth transistors (). The current sources () comprise fifth and sixth transistors (). The second circuits () further comprise voltage sources () further current sources. Third circuits () compensate common mode currents.

Device comprising a feedback-less gain controlled amplifier

The present invention provides a driving circuit () in particular for driving a laser diode () or a modulator, at data speed in the order of Gb/s. The driving circuit () has a low-voltage, high-speed output stage capable of driving efficiently a laser diode () or a modulator The driver circuit () comprises a chain of circuits, said chain comprising a slew-rate control circuit, at least one translinear amplifier (), a push/pull stage (), and an output stage () for driving the load current. Due to its versatility, the driver can be used in other applications e.g. line drivers, cable drivers, high-speed serial interfaces for back-plane interconnect, etc. The driver can work at low supply voltages, e.g. 3.3V nominal down to 2.7V, with high power efficiency. One major clue is to use entirely the large signal current produced by the output stage, e.g. in the driven laser diode, without wasting current in supply lines.

Low voltage, high-speed output-stage for laser or modulator driving

A BALUN circuit () for low voltage operation for receiving single ended input signal at an input terminal () and providing a differential output signal across a pair of output terminals (OUT+, OUT&#x2212;) is disclosed. The BALUN circuit () comprises a first branch including an input terminal () for receiving a single ended input voltage signal (RFin), a transistor (Q), a resistance (R) (), a resistance (RL), and an output terminal (OUT+). A second branch includes a transistor (Q), a resistance (RL) and an output terminal (OUT&#x2212;). An operational amplifier () maintains current flowing through the resistances RL in the first and second branches substantially equal to each other, in dependence upon the output voltage signal across the output terminals (OUT+, OUT&#x2212;).

Transformer circuit

The present invention relates to a detector arrangement and a charge pump circuit for a recovery circuit recovering timing information for random data. The detector arrangement comprises a first latch circuit for sampling a quadrature component of a reference signal based on an input signal, to generate a first binary signal, a second latch circuit for sampling an in-phase component of the reference signal based on the input signal, to generate a second binary signal, and a third latch circuit for sampling the first binary signal based on the second binary signal, to generate a frequency error signal. Furthermore, the charge pump circuit comprises a differential input circuit and a control circuit for controlling a tail current of the differential input circuit in response to a frequency-locked state of frequency detector arrangement.

A sub-harmonic mixer circuit having an input stage () and a current modulating stage (is disclosed. The input stage () receives an RF input signal (RF+, RF&#x2212;) at a first frequency and generates output currents (il , i) varying in dependence upon the Rf input signal. The current modulating stage () comprises a first transistor (Q) for receiving a first local oscillator signal (LO) respective and a second transistor (Q) for receiving a second local oscillator signal (LO), 180 degrees out of phase with the first local oscillator signal, such that a modulating current signal (iO), having twice the local oscillator frequency is superimposed onto the output currents.

Mixer circuit

A latch circuit comprising, a differential input with a non-inverting input (D+) and an inverting input (D&#x2212;). The latch further comprises a differential output with a non-inverting output (Q+) and an inverting output (Q&#x2212;). One of the outputs (Q&#x2212;) is coupled to one of the inputs input (D+) having an opposite polarity. The latch further comprises a control input for receiving a control signal (V) for determining a threshold for an input signal (In) such that if the input signal is at larger than the threshold the non-inverting output is in a HIGH logic state and in a LOW state if the input signal is smaller than the threshold.

Latch circuit

Polyphase filters comprise a plurality of filters each filter having passive elements. The filters are provided with integrators comprising amplifiers with admittance elements in feedback paths to create one or more other poles not situated on the negative imaginary axis in the plane-zero plot. A conductance element couples an output of an integrator of the integrators to an input of a previous integrator for introducing a frequency shift for at least one pole in the plane pole-zero plot. A capacitor couples an output of the integrator to an input of a next integrator for improving the quality factor of the polyphase filter. A signal inversion allows conductance elements to have negative values necessary for locating at least one pole at the most optimal location in the plane pole-zero plot.

Polyphase filter with integrators

The invention relates to a mixer circuit comprising an input node for receiving an input signal, a first output node, and a second output node, voltage to current conversion means and switching means operatively coupled to each other and to the input node, the first output node and the second output node to generate a mixed input signal at the first output node and the second output node in response to an oscillator signal. In an embodiment the voltage to current conversion means comprises a first and a second voltage to current converter, implemented as N-MOSFETs Mand M, with their gates connected to the input node. The drain of Mis connected to the first output node, while the drain of the Mis connected to the second output node M. The source of Mis connected to the switching node, while the source of Mis connected to the second switching node. The switches SW are arranged to couple the first switching nodeto a first supply voltage VDD and the second switching nodeto a second supply voltage VSS during a first phase of the oscillator signal, and the first switching nodeto VDD and the second switching nodeto VSS during a second phase of the oscillator signal. The mixer circuit according to the invention may operate at low supply voltages by using switches connected only to the supply voltages VSS and VDD. Mixing is achieved by voltage to current converters GMand GM, which are alternatingly activated by the switches SW.

Mixer circuit, receiver comprising a mixer circuit, wireless communication comprising a receiver, method for generating an output signal by mixing an input signal with an oscillator signal

A track and hold circuit () comprising:&#x2014;a linear amplifier () receiving a differential analog signal (D+, D&#x2212;) and being controlled by a first binary clock signal (H+) having a first phase,&#x2014;the linear amplifier () providing a feed-forward input signal substantially equal with the differential analog signal (D+, D&#x2212;) to a pseudo latch circuit () in the first phase of the first binary clock signal (H+), said pseudo latch circuit () being controlled by a second binary clock signal (H&#x2212;) for memorizing the input signal and providing a differential output signal (LD+, LD&#x2212;) substantially equal with the input signal during a second phase of the first binary clock signal (H&#x2212;), the second binary clock signal being substantially in antiphase with the first binary clock signal (H+).

Track and hold circuit

A tracking data cell () comprising:&#x2014;a pair of track and hold circuits (') coupled to a first multiplexer (),&#x2014;a clock signal (H+, H&#x2212;) being inputted substantially in anti-phase in the respective track and hold circuits (&#x2032;) for determining a receipt of a data signal (D+, D&#x2212;) having a rate, &#x2014;said track and hold circuits (&#x2032;) providing an output signal (O) having a substantially half rate.

Growing community of inventors

Eindhoven, Netherlands

Eduard Ferdinand Stikvoort