International Business Machines Corporation

Globalfoundries Inc.

Tokyo Electron Limited

Globalfoundries U.S. 2 LLC

Interuniversitair Micorelektronica Centrum (Imec, Vzw)

Eduard Albert Cartier

Vijay Narayanan

Takashi Ando

Vamsi Krishna Paruchuri

Evgeni Petrovich Gousev

Supratik Guha

Martin Michael Frank

Rajarao Jammy

Paul Charles Jamison

Matthew Warren Copel

Nestor A Bojarczuk, Jr

Barry P Linder

Bruce Bennett Doris

Kisik Choi

Cyril Cabral, Jr

Fenton Read McFeely

Harald F Okorn-Schmidt

Hemanth Jagannathan

Keith Kwong Hon Wong

Yanfeng Wang

Arne Watson Ballantine

Michael Patrick Chudzik

Herbert Lei Ho

Dirk Pfeiffer

Douglas Andrew Buchanan

Devendra K Sadana

Ghavam G Shahidi

Chung H Lam

Dechao Guo

Kevin K Chan

Douglas Duane Coolbaugh

Daniel Joseph Friedman

Chandrasekharan Kothandaraman

Ramachandran Muralidhar

Brian Joseph Greene

Renee Tong Mo

Hiroyuki Miyazoe

Frank Robert Libsch

Robert L Wisnieff

Richard Harold Boivie

Alessandro Cesare Callegari

Seiji Munetoh

Kohji Hosokawa

Charanjit Singh Jutla

Christopher Peter D'Emic

Young-Hee Kim

Wanki Kim

Anthony K Stamper

Veeraraghavan S Basker

Ying Di Zhang

Soon-Cheon Seo

Hariklia Deligianni

Kern Rim

Paul Michael Solomon

Joel Pereira De Souza

Amlan Majumdar

Qingqing Liang

Marwan H Khater

Babar Ali Khan

Sufi Zafar

Huiming Bu

Kandabara N Tapily

Jin Cai

Wagdi William Abadeer

Steven John Koester

Dexin Kong

Rishikesh Krishnan

Thomas George Ference

Naim Moumen

Kathryn Wilder Guarini

Yue Liang

Cory Wajda

Alessandro Curioni

Youngseok Kim

Huiling Shang

Kangguo Cheng

Alexander Reznicek

Jeffrey P Gambino

Oleg Gluschenkov

Sivananda K Kanakasabapathy

Katherine Lynn Saenger

Richard Stephan Wise

Ravikumar Ramachandran

Thomas W Dyer

Unoh Kwon

Peilin Song

Siddarth A Krishnan

Richard Alan Haight

Franco Stellari

James N Pan

Chao Zhao

Kathryn Turner Schonenberg

Gary A Tressler

Jean Fompeyrine

John Rozen

Adam J McPadden

Joseph Francis Shepard, Jr

Stefan Abel

Xi Li

Patrick Ronald Varekamp

Embodiments of the invention provide a resistive switching device that includes a metal interconnect electrode and a charge-particle-treated memory stack over the metal interconnect electrode. The charge-particle-treated memory stack includes a plurality of layers that includes a top electrode, a bottom electrode, and a dielectric layer between the top electrode and the bottom electrode. The dielectric layer includes a portion of a blanket dielectric layer. The bottom electrode includes a portion of a blanket bottom electrode layer. The charge-particle-treated memory stack further includes a current-conducting filament characteristic that results from charge particle treatments applied while a top surface of the blanket dielectric layer is exposed and a top surface of the blanket bottom electrode is exposed.

Oxide-based resistive memory having a plasma-exposed bottom electrode

A method of controlling the forming voltage of a dielectric film in a resistive random access memory (ReRAM) device. The method includes depositing a dielectric film contains intrinsic defects on a substrate, forming a plasma-excited treatment gas containing Hgas, and exposing the dielectric film to the plasma-excited treatment gas to create additional defects in the dielectric film without substantially changing a physical thickness of the dielectric film, where the additional defects lower the forming voltage needed for generating an electrically conducting filament across the dielectric film. The dielectric film can include a metal oxide film and the plasma-excited treatment gas may be formed using a microwave plasma source.

Method for controlling the forming voltage in resistive random access memory devices

Provided are embodiments for a semiconductor device. The semiconductor device includes a bottom electrode, wherein the bottom electrode is formed on a metal interconnect electrode, and a dielectric layer on a surface of the bottom electrode. The semiconductor device also includes a top electrode formed on a surface of the dielectric layer, wherein at least one of the top electrode or the bottom electrode is a plasma treated top electrode or plasma treated bottom electrode. Also provided are embodiments for a method of fabricating a resistive switching device where at least one of the plurality of layers of the memory stack is processed with a charge particle treatment.

Embodiments of the present invention are directed to a back-end-of-line (BEOL) compatible metal-insulator-metal on-chip decoupling capacitor (MIMCAP). This BEOL compatible process includes a thermal treatment for inducing an amorphous-to-cubic phase change in the insulating layer of the MIM stack prior to forming the top electrode. In a non-limiting embodiment of the invention, a bottom electrode layer is formed, and an insulator layer is formed on a surface of the bottom electrode layer. The insulator layer can include an amorphous dielectric material. The insulator layer is thermally treated such that the amorphous dielectric material undergoes a cubic phase transition, thereby forming a cubic phase dielectric material. A top electrode layer is formed on a surface of the cubic phase dielectric material of the insulator layer.

Back-end-of-line compatible metal-insulator-metal on-chip decoupling capacitor

Methods and systems for locating a filament in a resistive memory device are described. In an example, a device can acquire an image indicating an occurrence of photoemission from the resistive memory device. The device can determine a location of the filament in a switching medium of the resistive memory device using the acquired image.

RRAM filament location based on NIR emission

A semiconductor structure, and a method of making the same includes a multiple electrode stacked capacitor containing a sequence of first metal layers interleaved with second metal layers. A quad-layer stack separates each of the first metal layers from each of the second metal layers, the quad-layer dielectric stack includes a first dielectric layer made of AlO, a second dielectric layer made of HfO, a third dielectric layer made of AlO, and a fourth dielectric layer made of HfO.

Quad-layer high-k for metal-insulator-metal capacitors

A resistive random access memory (RERAM) apparatus and method for forming the apparatus are provided. Oxygen content control in the RERAM is provided. To provide oxygen content control, a via to an electrode of the RERAM is formed utilizing an oxygen-free plasma etch step. In one embodiment, the dielectric within which the via is formed is silicon nitride (SiN). In exemplary embodiments, the plasma chemistry is a hydrofluorocarbon (CHF)-based plasma chemistry or a fluorocarbon (CF)-based plasma chemistry. In one embodiment, the resistive layer of the RERAM is a metal oxide. In another embodiment, the oxygen concentrations in the electrode of the RERAM under the via and outside the via are the same after formation of the via.

Oxygen-free plasma etching for contact etching of resistive random access memory

A private key of a public-private key pair with a corresponding identity is written to an integrated circuit including a processor, a non-volatile memory, and a cryptographic engine coupled to the processor and the non-volatile memory. The private key is written to the non-volatile memory. The integrated circuit is implemented in complementary metal-oxide semiconductor 14 nm or smaller technology. The integrated circuit is permanently modified, subsequent to the writing, such that further writing to the non-volatile memory is disabled and such that the private key can be read only by the cryptographic engine and not off-chip. Corresponding integrated circuits and wafers are also disclosed.

Encryption engine with an undetectable/tamper-proof private key in late node CMOS technology

A method of forming a semiconductor device that includes forming a metal oxide material on a III-V semiconductor channel region or a germanium containing channel region; and treating the metal oxide material with an oxidation process. The method may further include depositing of a hafnium containing oxide on the metal oxide material after the oxidation process, and forming a gate conductor atop the hafnium containing oxide. The source and drain regions are on present on opposing sides of the gate structure including the metal oxide material, the hafnium containing oxide and the gate conductor.

Structures and methods for equivalent oxide thickness scaling on silicon germanium channel or III-V channel of semiconductor device

A method for forming a metal-insulator-metal (MIM) capacitor on a semiconductor substrate is presented. The method includes forming a first electrode defining columnar grains, forming a dielectric layer over the first electrode, and forming a second electrode over the dielectric layer. The first and second electrodes can be titanium nitride (TiN) electrodes. The dielectric layer can include one of hafnium oxide and zirconium oxide deposited by atomic layer deposition (ALD). The ALD results in deposition of high-k films in grain boundaries of the first electrode.

Surface area enhancement for stacked metal-insulator-metal (MIM) capacitor

Encryption engine with an undetectable/tamper proof private key in late node CMOS technology

A tri-layer dielectric stack is provided for a metal-insulator-metal capacitor (MIMCAP). Also, a metal-insulator-metal capacitor (MIMCAP) is provided having three or more electrodes. The tri-layer dielectric stack includes a first layer formed from a first metal oxide electrical insulator. The tri-layer dielectric stack further includes a second layer, disposed over the first layer, formed from ZrO. The tri-layer dielectric stack also includes a third layer, disposed over the second layer, formed from a second metal oxide electrical insulator.

Multilayer dielectric for metal-insulator-metal capacitor (MIMCAP) capacitance and leakage improvement

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New York, NY, United States of America

Eduard Albert Cartier