Vmware, Inc.

Leland Stanford Junior University

Edouard Bugnion

Scott W Devine

Mendel Rosenblum

Beng-Hong Lim

Carl Alan Waldspurger

Pratap Subrahmanyam

Ole Agesen

Bich Cau Le

A source computer system with one instruction set architecture (ISA) is configured to run on a target hardware system that has its own ISA, which may be the same as the source ISA. In cases where the source instructions cannot be executed directly on the target system, the invention provides binary translation system. During execution from binary translation, however, both synchronous and asynchronous exceptions may arise. Synchronous exceptions may be either transparent (requiring processing action wholly within the target computer system) or non-transparent (requiring processing that alters a visible state of the source system). Asynchronous exceptions may also be either transparent or non-transparent, in which case an action that alters a visible state of the computer system needs to be applied. The invention includes subsystems, and related methods of operation, for detecting the occurrence of all of these types of exceptions, to handle them, and to do so with precise reentry into the interrupted instruction stream; by 'precise' is meant that the atomic execution of the source instructions is guaranteed, and that the application of actions, including those that originate from asynchronous exceptions, occurs at the latest at the completion of the current source instruction at the time of the request for the action. The binary translation and exception-handling subsystems are preferably included as components of a virtual machine monitor which is installed between the target hardware system and the source system, which is preferably a virtual machine.

Binary translator with precise exception synchronization mechanism

According to one aspect of the invention, a request to generate a state checkpoint of a computer is initiated within a user-level software entity, such as a virtual machine. Upon sensing the request, a checkpointing mechanism generates and stores at least one checkpoint, each checkpoint comprising a representation of the total state of the computer system. Upon sensing a state restoration request corresponding to one of the checkpoints, the checkpointing mechanism restores the checkpointed state in the computer, which can then resume operation from the restored total state. According to another aspect of the invention, a total checkpointed state is exported to another computer, where the state can be modified, for example, debugged, and then loaded into either the originally checkpointed computer (which, again, may be a virtual machine), or some other computer.

Mechanism for providing virtual machines for use by multiple users

A source computer system with one instruction set architecture (ISA) configured to run on a target hardware system that has its own ISA. During execution from binary translation, synchronous exceptions may be either transparent (requiring processing action wholly within the target computer system) or non-transparent (requiring processing that alters a visible state of the source system, and asynchronous exceptions may also be either transparent or non-transparent, in which case an action that alters a visible state of the computer system needs to be applied. The system also includes subsystems, and related methods of operation, for detecting the occurrence of all of these types of exceptions, to handle them, and to do so with precise reentry into the interrupted instruction stream. The binary translation and exception-handling subsystems are included as components of a virtual machine monitor which is installed between the target hardware system and the source system.

I/O operations between a virtual machine (VM) and a device external to the VM are monitored by a virtual machine monitor (VMM). Data passing between the VM and the external device is transformed by the VMM, in some cases only when a predetermined filtering or triggering condition is met. Because the VMM, and thus the transformation operation, is transparent to the VM, the transformation cannot be prevented or undone or even affected by any action by a user of the VM. Examples of the non-defeatable transformation of I/O data include generating display overlays such as banners, masking out portions of a display, encryption, compression and network shaping such as bandwidth limiting.

Undefeatable transformation for virtual machine I/O operations

The invention virtualizes a computer that includes a host computer system, which comprises a processor, memory, and physical system devices. A conventional operating system (referred to below as the 'host operating system' or 'HOS') is installed on the hardware. A computer program product that is executable within the host computer system comprises computer-executable code for implementing an interface software layer, preferably a virtual machine monitor, between the host system and a virtual machine; for reading in and storing state information of the processor associated with the HOS; and for logically decoupling the HOS from the processor with respect to pre-determined functions of the interface software layer and the virtual machine by setting the processor state information to settings associated with the interface software layer.

Context-switching to and from a host OS in a virtualized computer system

A computer system includes at least one virtual machine that has a plurality of virtual processors all running on an underlying hardware platform. A software interface layer such as a virtual machine monitor establishes traces on primary structures located in a common memory space as needed for the different virtual processors. Whenever any one of the virtual processors generates a trace event, such as accessing a traced structure, then a notification is sent to at least the other virtual processors that have a trace on the accessed primary structure. In some applications, the VMM derives and maintains secondary structures corresponding to the primary structures, such as where the VMM converts, through binary translation, original code intended to run on a virtual processor into code that can be run on an underlying physical processor of the hardware platform. In these applications, the VMM may rederive or invalidate the secondary structures as needed upon receipt of the notification of the trace event. Different semantics are provided for the notification, providing different choices of performance versus guaranteed consistency between primary and secondary structures. In the preferred embodiment of the invention, a dedicated sub-system is included within the VMM for each virtual processor; each sub-system establishes traces, senses trace events, issues the notification, and performs other operations relating specifically to its respective virtual processor.

System and method for detecting access to shared structures and for maintaining coherence of derived structures in virtualized multiprocessor systems

A virtual machine monitor (VMM) is included in a computer system that has a protected host operating system (HOS). A virtual machine running at least one application via a virtual operating system is connected to the VMM. Both the HOS and the VMM have separate operating contexts and disjoint address spaces, but are both co-resident at system level. A driver that is downloadable into the HOS at system level forms a total context switch between the VMM and HOS contexts. A user-level emulator accepts commands from the VMM via the system-level driver and processes these commands as remote procedure calls. The emulator is able to issue host operating system calls and thereby access the physical system devices via the host operating system. The host operating system itself thus handles execution of certain VMM instructions, such as accessing physical devices.

System and method for facilitating context-switching in a multi-context computer system

A computer system is interrupted, and its entire state information is extracted as one or more checkpoints at one or more respective points during operation of the system. The checkpoint may be restored into the system at any later time, even multiple times, and it may also even be loaded into one or more other systems; all systems loaded with the same checkpoint will then execute from the same checkpointed state. The state extraction mechanism is preferably a virtual machine monitor, on which one or more virtual machines are installed, each virtual machine constituting an encapsulated, virtualized computer system whose states can be checkpointed under control of the virtual machine monitor. Checkpoints may be stored on a portable memory device or transmitted as a batch or dynamically over a network so that even virtual machines installed at different sites may execute from the same state.

Mechanism for restoring, porting, replicating and checkpointing computer systems using state extraction

One or more virtual machines (VM's) run via a virtual machine monitor (VMM) on a hardware platform that has a segmented memory architecture. Each VM has at least one VM descriptor table that has, as entries, VM segment descriptors. At least one VMM descriptor table is established, including at least one shadow descriptor table that stores shadow descriptors for certain of the VM segment descriptors, which are then shadowed descriptors. The VMM compares the shadow descriptors with their respective corresponding shadowed VM descriptors, detects any lack of correspondence between the shadow descriptor table and the corresponding VM descriptor table, and updates and thereby synchronizes each shadow descriptor with its respective shadowed VM descriptor no later than, and preferably only upon the first use of, the respective descriptor by the VM. Whenever the VMM detects any attempt by the VM to load an usynchronized shadowed descriptor, the VMM verifies that the VM is allowed to load it, and then establishes synchronization for the pair of descriptors. One detection mechanism is the tracing of entire memory pages in which VM descriptors are stored; another involves sensing and setting the state of a segment present bit for individual descriptors. The invention improves virtualization performance by reducing the number of descriptors that need to be kept coherent. The VMM also has a flexible mechanism to invalidate descriptors, for example, when the VM unmaps or remaps the memory page it is located in, or when the VM sets a new segment descriptor table.

Deferred shadowing of segment descriptors in a virtual machine monitor for a segmented computer architecture

A dynamic binary translator converts input instruction sequences into output instruction sequences that are stored in a translation cache. In order to maintain coherence of the translation cache with the run-time version of the input instructions, translated code is checked by either a conflict detection mechanism or a code-invariance mechanism. For conflict detection, the system preferably uses memory traces generated by the memory management unit of the underlying hardware processor. In order to check for code-invariance, preludes for comparing cached, output instruction sequences with their supposed run-time input instruction equivalents are appended to the cached instructions themselves. Changes in the input sequences then result only in retranslation of instruction sequences in which at least one instruction has changed; this avoids costly total flushes of the translation cache. An additional prelude is appended to any cached output sequences displaying characteristics of potentially self-constant-modifying code. If the input instructions have since translation changed with respect only to constants, then the constants are updated before execution; this completely eliminates the need for flushing the translation cache or retranslating the instruction if only constants have changed since the original translation. The invention is preferably incorporated in a virtual machine monitor, on which a virtual machine is running.

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Palo Alto, CA, United States of America

Edouard Bugnion