Infineon Technologies Ag

Qimonda Ag

Lantiq Deutschland Gmbh

Edoardo Prete

Anthony Sanders

Dirk Scheideler

Georg Braun

Richard Johannes Luyken

Steve Wood

Hans-Peter Trost

Peter Gregorius

Karthik S Gopalakrishnan

Paul Wallner

Hamid Partovi

Luca Ravezzi

Sivaraman Chokkalingam

Philipp Börker

Dirk Friebe

David Müller

Volkmar Rebmann

Claudio Andreotti

David M&uuml;ller

Bruno Celli-Urbani

An apparatus for providing a signal for transmission via a signal line includes a controller circuit having an output for a signal indicating whether the signal line is or will be in an inactive state and a switching circuit coupled to the controller circuit and having an output coupled to the signal line. The output is switched between different signal levels, if the signal indicates that the signal line is in an inactive state.

Apparatus and method for providing a signal for transmission via a signal line

An arrangement for generating a transmission clock signal and a reception clock signal is proposed in which only a single voltage-controlled oscillator is used, the reception clock signal being generated by phase-adjusting means whereas the transmission clock signal is generated directly by the voltage-controlled oscillator. Cross-talk between a plurality of voltage-controlled oscillators can be prevented in this way. Also, various measures are proposed for optimizing a circuit of this kind.

Generating a transmission clock signal and a reception clock signal for a transceiver using an oscillator

A data sampler including a first stage and a second stage. The first stage is configured to receive differential signals and provide a first edge rate in a first output signal and a second edge rate in a second output signal based on the differential signals. The second stage is configured to amplify the difference between the first output signal and the second output signal to provide regenerated output signals. The second stage provides a third edge rate in a first internal signal and a fourth edge rate in a second internal signal based on the first edge rate and the second edge rate.

Data sampler including a first stage and a second stage

An apparatus being connectable as a latch stage into a asynchronous latch chain comprises a reception interface, wherein upon receipt of the first signal at the reception interface, the apparatus switches to one of the first power saving mode and a second power saving mode, depending on the second signal at the reception interface and wherein the apparatus offers a first power consumption and a first wake-up time in the first power saving mode, and a second power consumption and a second wake-up time in the second power saving mode.

Apparatus and method for switching an apparatus to a power saving mode

A clock and data recovery circuit includes a phase detector configured to compare a phase of a data signal to a phase of a sampling clock to provide a phase error signal, a gain stage configured to apply a gain to the phase error signal to provide an amplified phase error signal, and a filter configured to filter the amplified phase error signal to provide a phase correction signal. The circuit includes a gain controller configured to adjust the gain of the gain stage in response to the phase correction signal, and a clock generator configured to provide the sampling clock based on the phase correction signal.

Clock and data recovery circuit having gain control

A clock signal extraction device for extracting a clock signal from a periodic data signal includes a phase detector for detecting a first phase difference between rising edges of said data signal and a rising edges clock signal and for detecting a second phase difference between falling edges of said data signal and a falling edges clock signal. The device also includes a clock generator for generating said rising edges clock signal so that said first phase difference is minimized, for generating said falling edges clock signal so that said second phase difference is minimized, and for generating said clock signal in dependence on said first phase difference and said second phase difference. A method for extracting a clock signal from a periodic data signal is related to the device.

Clock signal extraction device and method for extracting a clock signal from data signal

Method and arrangement for generating an output clock signal with an adjustable phase relation from a plurality of input clock signals. A method and an arrangement are provided for generating an output clock signal (o), in which a plurality of input clock signals (s, c) that have a predetermined phase relationship to one another, are weighted with respective weighting factors (A,-A), and in which the weighted input clock signals (s', c&#x2032;) are added in order to generate a summated clock signal (i). The summated clock signal (i) is integrated in an integrator () and optionally amplified in order to generate the output clock signal (o). An output clock signal (o) with an adjustable phase relation can be generated with such a method and such an arrangement, in which the requirements placed on the input clock signals are less stringent.

Method and arrangement for generating an output clock signal with an adjustable phase relation from a plurality of input clock signals

An apparatus interfaces a first circuit using a first supply voltage and a second circuit using a second supply voltage different from the first supply voltage. The apparatus includes a driver circuit having a driver network comprising driver supply voltage terminals connected to controllable switches. The controllable switches include resistive elements or are separated from resistive elements. A receiver circuit has a receiving network comprising a resistive element and receiver supply voltage terminals and a connection line connecting the driver circuit and the receiving circuit. The controllable switches have two switch configurations, a first switch configuration resulting in a high voltage on the connection line and a second switch configuration resulting in a low voltage on the connection line.

Concept for interfacing a first circuit requiring a first supply voltage and a second supply circuit requiring a second supply voltage

The present invention relates to a method and apparatus for generating an output signal in dependence on a phase difference between two periodic signals. The present invention is particularly useful in phase locked loops and delay locked loops, in which a controllable oscillator or a controllable delay device is controlled on the basis of the phase difference determined by means of phase detection, in such a way that a control signal can be obtained, the phase lag or frequency of which has a firm relationship to the reference signal.

Method and apparatus for phase detection

To generate an output signal ( ) the frequency of which is twice the frequency of an input signal ( ), a delayed signal ( ) which is delayed relative to the input signal ( ) by a quarter of the latter's cycle period is generated and the output signal ( ) is then generated as the difference between the rectified input signal ( ) and the rectified delayed signal ( ). The input signal ( ) and the delayed signal ( ) are advantageously rectified by using differential signals each comprising a positive component signal ( ) and a negative component signal ( ). A respective one of two transistors connected in parallel is driven by a positive component signal ( ) and a negative component signal ( ) in such a way that a positive half-wave causes the relevant transistor ( ) to conduct and the relevant transistor ( ) blocks in a negative half-wave. The rectified input signal ( ) or delayed signal ( ) is obtained from the two component currents flowing through the pairs of transistors ( ) connected in parallel when the currents are added. The rectified input signal ( ) and delayed signal ( ), which are in the form of current signals, can be passed through two resistors ( ) to enable corresponding voltage signals to be generated across the latter and the output signal ( ) to be picked off from the two resistors ( ).

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Munich, Germany

Edoardo Prete