Hewlett-Packard Company

Avago Technologies General IP (Singapore) Pte. Ltd.

Other

Agilent Technologies, Inc.

Palau Acquisition Corporation (Delaware)

Edmundo Rojas

S Paul Tucker

Theodore G Rossin

Glenn W Strunk

Alan S Krech, Jr

Jon L Ashburn

Mercedes E Gil

Ted Scott Rakel

Michael S McGrath

Hui-Sian Ong

Robert H Miller, Jr

Richard L Schober, Jr

Ian G Colloff

Norman C Chou

Zhang Xiaoyang

A method and structure for the handling and discarding of packets in a packet data network. The method includes a packet data network receiving one or more packets from one or more remote locations and initiating a transfer of a packet of the one or more packets to a remote destination. The remote destination is operable to act as a destination port of a switch. The transfer of the packet is initiated while the packet of the one or more packets is being received, and the packet validity is also checked while the transfer of the packet is initiated. If the packet is invalid, the transfer of the packet of the one or more packets to the remote destination is canceled. Determining packet validity includes inspection of a packet header. The structure has a receive link determining packet validity and passing this error signal to a packet processor. The packet processor has a packet transfer request generator, a packet checker, packet reader, packet memory and tag memory. The packet transfer request generator initiates a transfer request over a switch with a remote destination. While the request is processed, the packet checker verifies packet correctness and stores the packet data for transmission to the remote destination. If a packet is in error, a bad tag is set and the packet transfer is aborted.

Handling and discarding packets in a switching subnetwork

In general, a system and method for providing data packet flow control is disclosed. Generally, a switch is provided that contains a series of ports, an arbiter and a hub. The arbiter determines an outgoing port, wherein the outgoing port is one port for the series of ports, for transmission of a data packet received by the switch, determines whether the outgoing port is available to receive the received data packet, and regulates transmission of the received data packet to a destination end node. The hub provides a point-to-point connection between any two of the series of ports and the arbiter.

Systems and methods for providing data packet flow control

A switch for use with an InfiniBand network. The switch includes a crossbar that redirects packet-based data based on a forwarding table. At least one port that receives data from a network and selectively transfers that data to the crossbar using a variable number of virtual lanes. A state machine controls the changing of the number of virtual lanes.

Apparatus and methods for dynamic reallocation of virtual lane buffer space in an infiniband switch

A networking system includes a plurality of ports, each adapted to send and receive data. A switch core has a first channel configured to receive a logical input flow from each of the plurality of input ports, and has a second channel configured to receive a raw input flow from each of the plurality of input ports. Each logical input flow is carried by its corresponding raw input flow. A plurality of port mirrors are selectable from the plurality of ports. Each of the plurality of port mirrors is configured to produce a duplicate copy of at least one of the logical input flow and the raw input flow available at a selected port.

Method and apparatus for input/output port mirroring for networking system bring-up and debug

A method and apparatus for operating a memory is presented. Information is stored in the memory based on a first time domain and information is read from the memory based on a second time domain. A cooperative relationship is maintained between a write pointer which points to memory locations, where data will be stored and a read pointer which points to memory locations, from which data will be read. A FIFO memory is presented which has memory locations and a register array is presented which stores a bit array that has bit locations. Each bit location in the bit array corresponds to a memory location in the memory. As the write pointer points to a memory location and data is stored in the memory location, a bit (e.g. flag) is set in the bit array. The Flag designates whether the data stored in the memory location is available for reading. Prior to reading information from the memory location, a test is made of the bit location that corresponds to the memory location. The bit value denotes whether the data stored in the memory location is valid data and available for reading.

Method and apparatus for asynchronous read control

A method and apparatus for managing a communication system including multiple links is presented. A receiver including a First-In, First-out (FIFO) memory receives information communicated on the links. A FIFO is associated with each communication link. Information is written into the FIFO based on a transmitter clock. Information is read out of the FIFO using a receiver clock. The FIFO is used to deskew data communicated across the communication links and re-synchronize the data between the transmitter clock and the receiver clock. A state machine controls the information read out of the FIFO. The state machine includes a deskew enabled state, a deskew disabled state and a reset state. Using the FIFO, the system is able to self reset and transition between the deskew enabled state and the deskew disabled state.

System comprising a state machine controlling transition between deskew enable mode and deskew disable mode of a system FIFO memory

The invention provides for a system and method for minimizing space requirements and increasing speed in a geometry accelerator for a computer graphics system. In architecture, the system is implemented as follows. The geometry accelerator includes a plurality of processing elements (e.g., an arithmetic logic unit, a multiplier, a divider, a compare mechanism, a clamp mechanism, etc.) and a plurality of control units (e.g., a transform mechanism, a decomposition mechanism, a clip mechanism, a bow-tie mechanism, a light mechanism, a classify mechanism, a plane equation mechanism, a fog mechanism, etc.) that utilize the processing elements for performing data manipulations upon image data. In accordance with the invention, the control units are implemented in a read-only memory (ROM) via microcode. A next address field is associated with each of the microcode instructions and defines a location in the ROM of a next instruction to be executed. A plurality of control unit logic elements correspond respectively with the control units and control instruction branching within their respective control unit by defining the next address field. A branch central intelligence mechanism controls branching between the control units by defining the next address field.

ROM-based control unit in a geometry accelerator for a computer graphics system

The invention provides for a system and method for minimizing space requirements and increasing speed in a geometry accelerator for a computer graphics system by providing a branch central intelligence mechanism. Architecturally, the geometry accelerator includes a plurality of processing elements (e.g., an arithmetic logic unit, a multiplier, a divider, a compare mechanism, a clamp mechanism, etc.) and a plurality of control units (e.g., a transform mechanism, a decomposition mechanism, a clip mechanism, a bow-tie mechanism, a light mechanism, a classify mechanism, a plane equation mechanism, a fog mechanism, etc.) that utilize the processing elements for performing data manipulations upon image data. In accordance with the invention, the control units are implemented in a read-only memory (ROM) via microcode. A next address field is associated with each of the microcode instructions and defines a location in the ROM of a next instruction to be executed. A plurality of control unit logic elements correspond respectively with the control units and control instruction branching within their respective control unit by defining the next address field. Finally, a branch central intelligence mechanism controls branching between the control units by defining the next address field.

Centralized branch intelligence system and method for a geometry accelerator

A system and method for performing view clipping and model clipping of graphics primitives in a geometry accelerator of a computer graphics system. The method includes performing view clipping and model clipping of the graphics primitives in homogeneous window coordinates. The geometry accelerator includes a transform machine, a light machine, a clipping machine, and a plane equation machine. The transform machine receives vertex data defining a graphics primitive, in object coordinates, and transforms the vertex data into homogeneous window coordinates. The light machine receives the transformed vertex data from the transform machine and enhances the transformed vertex data by simulating lighting conditions of the graphics primitive. The light machine provides light enhanced transformed vertex data to the clipping machine. The clipping machine receives the light enhanced vertex data from the light machine and determines intersections of edges of the graphics primitive with view clipping planes and with any user specified model clipping planes. The resulting clipped vertex data from the clipping machine is provided to the plane equation machine. The plane equation machine calculates plane equations defining geometries formed by the clipped vertex data and provides the calculated plane equations to the computer graphics system for display.

Post transformation clipping in a geometry accelerator

ROM-based control units in a geometry accelerator for a computer

A system and method for reducing an amount of memory that is needed to perform view clipping and model clipping of an input primitive in a geometry accelerator of a computer graphics system. The method includes view clipping the input graphics primitive with each view clipping boundary to determine a view-clipped geometry, storing view-clipped vertex data defining the view clipped geometry in memory, model clipping a view-clipped triangle forming the view-clipped geometry with each user defined model clipping plane to determine a model-clipped geometry, and storing model-clipped vertex data defining the model-clipped geometry in the memory in the memory locations previously occupied by said view-clipped vertex data. The method is repeated until each view-clipped triangle forming the view-clipped geometry has been model-clipped.

Growing community of inventors

Fort Collins, CO, United States of America

Edmundo Rojas