Arm Limited

Edmund Thomas Grimley-Evans

Simon Andrew Ford

Alastair David Reid

Katherine Elizabeth Kneebone

A system and method are provided for translating a guest instruction of a guest architecture into at least one host instruction of a host architecture. The method comprises providing multiple representation states, each representation state providing a representation in the host architecture for at least one item of state from the guest architecture. A current representation state is then determined from amongst the multiple representation states, and the guest instruction is translated into at least one host instruction in dependence on the current representation state. Through the use of multiple representation states, it has been found that the efficiency of the code translation can be significantly increased, thereby giving rise to performance and energy consumption benefits.

System and method for translating a guest instruction of a guest architecture into at least one host instruction of a host architecture

A computer implemented tool is provided for assisting in the mapping of a computer program to a data processing apparatus wherein multiple physical instances of a logical variable in the computer program are required. A computer program is provided as the input to the tool which analyses the data flow of the program and identifies multiple physical instance requirement for logical variables. The tool adds mapping support commands, such as instantiation commands, Direct Memory Access (DMA) move commands and the like as necessary to support the mapping of the computer program to a data processing apparatus.

Variable coherency support when mapping a computer program to a data processing apparatus

A computer implemented tool is provided for assisting in the mapping of a computer program to an asymmetric multiprocessing apparatusincorporating an asymmetric memory hierarchy formed of a plurality of memories. An at least partial architectural descriptionis provided as an input variable to the tool and used to infer missing annotations within a source computer program, such as which functions are to be executed by which execution mechanismsand which variables are to be stored within which memories. The tool also adds mapping support commands, such as cache flush commands, cache invalidate commands, DMA move commands and the like as necessary to support the mapping of the computer program to the asymmetric multiprocessing apparatus

Mapping a computer program to an asymmetric multiprocessing apparatus

An asymmetric multiprocessor apparatusis provided in which respective slave diagnostic unitsare associated with corresponding execution mechanisms. A master diagnostic unittracks the migration of thread execution between the different execution mechanismsso that the execution of a given thread can be followed by the diagnostic mechanismsand this information provided to the programmer. The execution mechanismscan be diverse such as a general purpose processor, a DMA unit, a coprocessor, an VLIW processor, a digital signal processorand a hardware accelerator. The asymmetric multiprocessor apparatuswill also typically include an asymmetric memory hierarchy such as including two or more of a global memory, a shared memory, a private memoryand a cache memory.

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Cambridge, United Kingdom

Edmund Thomas Grimley-Evans