Xilinx, Inc.

Triscend Corporation

Other

Edmond Y Cheung

Charles R Erickson

Philip M Freidin

Hung-Cheng Hsieh

Brian Fox

Andreas Papaliolios

William S Carter

Steven Winegarden

Tsung-Lu Syu

Charles S Erickson

Fung Fung Lee

Wilson Kaming Yee

Hung-Cheng Hsieh, Deceased

By William Carter, Administrator

Charles R Erikson

The I/O circuit of the present invention provides optimal flexibility and performance using a number of different structures and methods. The present invention provides a signal follower circuit for an input pad. In one embodiment, the output buffer is capable of injecting a constant onto a pad during reconfiguration of a configurable system logic circuit. The present invention also provides a circuit for generating a programmable data propagation delay, thereby guaranteeing zero hold time for an arbitrary input register. Zero hold time is accomplished by allowing the user to optimally characterize clock delay to a given input/output circuit. The present invention also provides fast switching between input pads, thereby minimizing data propagation delay between the input pads. Additionally, the present invention reduces time spent in production product test by facilitating the testing of multiple routes with one test configuration. A circuit expanding the number of data input channels available to system routing is provided. Lastly, a plurality of identical input/output block tiles (IOBTs) is disclosed, thereby enabling each I/O circuit to provide the same signals regardless of the IOBTs location in the I/O circuit.

Input/output circuit with user programmable functions

A method and system for the rapid and precise configuration of a bank of logic in a configurable system on a chip. The configuration memory array is partitioned into a plurality banks. Configuration circuitry is implemented for each bank. This allows for the configuration of one or more banks while the other banks remain operable.

Bank-based configuration and reconfiguration for programmable logic in a system on a chip

A structure for providing clearing/programming includes a plurality of synchronous flip-flops, and a plurality of associated two-input multiplexers. A control signal in a first logic state provided to the multiplexers provides a first signal propagation direction through the flip-flops, whereas the control signal in a second logic state provides a second signal propagation direction through the flip-flops. One method for clearing and programming a programmable logic device includes arranging a plurality of memory cells in sets, clearing the sets in a first spatial sequence, and programming the sets in a second spatial sequence. Sets of memory cells could include columns of memory cells, each column having an associated storage element. In this manner, a plurality of columns of memory cells can be cleared or programmed in any predetermined order. Thus, a method for programming a logic device may include programming a plurality of columns of memory cells in a first direction, and then programming a another plurality of columns of memory cells in a second direction. A reverse order is preferably used for clearing that logic device. Note that within one plurality of columns, any spatial sequence could be provided.

Configuration logic to eliminate signal contention during reconfiguration

A method of eliminating signal contention during reconfiguration of a programmable logic device includes the steps of: arranging a plurality of memory cells in sets and selectively programming the memory cells one set at a time, either in a first direction or a second direction. A structure for providing that selective programming includes a plurality of synchronous flip-flops, and a plurality of associated two-input multiplexers. A control signal in a first logic state provided to the multiplexers provides a first signal propagation direction through the flip-flops, whereas the control signal in a second logic state provides a second signal propagation direction through the flip-flops.

A configurable logic block (CLB) in the dual port mode uses one address to write the same information in a first RAM and a second RAM. The input signals provided to the second function generator can be used to read, independently from and even asynchronously with, the write operation, thereby dramatically increasing the speed of applications using the two sets of RAM. A CLB in the synchronous mode latches the appropriate address and data signals, and generates a strobed write enable signal. The strobed signal is self-timed, i.e. the write operation is fully automatic, thereby ensuring that a write operation occurs within one clock cycle.

Synchronous dual port RAM

A method of eliminating signal contention during reconfiguration of a programmable logic device includes the steps of: arranging a plurality of memory cells in sets and selectively programing the memory cells one set at a time, either in a first direction or a second direction. A structure for providing that selective programming includes a plurality of synchronous flip-flops, and a plurality of associated two-input multiplexers. A control signal in a first logic state provided to the multiplexers provides a first signal propagation direction through the flip-flops, whereas the control signal in a second logic state provides a second signal propagation direction through the flip-flops.

Synchronous dual port ram

Programmable logic devices which include multiple blocks of combinatorial function generators and storage elements, and which are interconnected by a programmable interconnect structure are used, among other things for performing arithmetic functions which use logic for generating the carry function. When a large number of bits is to be processed, the carry function typically causes significant delay or requires significant additional components to achieve a result at high speed. The present invention provides dedicated hardware within the logic blocks for performing the carry function quickly and with a minimum number of components. The invention takes advantage of the fact that a carry signal to be added to two bits can be propagated to the next more significant bit when the two binary bits to be added are unequal, and that one of the bits can serve as the carry signal when the bits are equal.

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San Jose, CA, United States of America

Edmond Y Cheung