Meta Platforms Technologies, LLC

Edith Dallard

Daniel Henry Morris

Huichu Liu

Fan Wu

An SRAM controller for performing sequential accesses using internal ports that operate concurrently on different rows. Each internal port includes a row address strobe (RAS) timer that generates clock signals controlling the timing of operations during a RAS phase in which word line decoding is performed once for a group of bit cells being accessed. The RAS phase can involve additional conditioning operations, such as precharging of local bits lines associated with the group of bit cells. The RAS phase is followed by an input/output (IO) phase in which individual bit cells are accessed in sequential address order using a column select signal generated by an IO timer. The RAS phase of a first internal port can be at least partially overlapped by the IO phase of a second internal port to hide the RAS latency of the first internal port. The IO timer can be shared among internal ports.

SRAM design for energy efficient sequential access

Methods and corresponding systems and apparatuses for saving power through selectively disabling clock signals in a systolic array are described. In some embodiments, a clock gate controller is operable to output a gated clock signal from which local clock signals of processing elements in the systolic array are derived. The gated clock signal corresponds to a root clock signal that is distributed through a clock distribution network or clock tree. The clock gate controller is located along one branch of the clock distribution network. The branch can be associated with processing elements that form a column within the systolic array. Disabling the gated clock signal disables the local clock signals along the entire branch, preventing any components that are clocked by those local clock signals from consuming power. Additional clock gate controllers can similarly be provided for other branches, including a branch associated with another column.

Data-driven column-wise clock gating of systolic arrays

In some embodiments, a system comprises a static random access memory (SRAM) device and a controller. The SRAM device comprises a bit cell array comprising a plurality of bit cells arranged in a plurality of rows and a plurality of columns, each column operatively coupled to a pair of bit lines, wherein the plurality of columns is arranged as a plurality of column groups each comprising a plurality of local columns. The SRAM device further comprises a plurality of column decoders, each associated with a column group of the plurality of column groups. In some embodiments, the controller may be configured to read the local columns included in the column group by, for a given local column, sensing a voltage difference on a corresponding pair of bit lines, in a rearranged sequential order that is different from a physical sequential order of the plurality of local columns.

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San Mateo, CA, United States of America

Edith Dallard