Commissariat &#xc0; L'&#xc9;nergie Atomique Et Aux &#xc9;nergies Alternatives

Commissariat a L'energie Atomique

Centre National De La Recherche Scientifique

Universitè De Montpellier

Institut National Polytechnique De Grenoble

Politecnico Di Torino

Université Montpellier 2 Sciences Et Techniques

Edith Beigne

Pascal Vivet

Grégory Di Pendina

Sylvain Miermont

Eldar Zianbetov

Jean-Pierre Rostaing

Suzanne Lesecq

Fabien Clermidy

Diego Puschini Pascual

Marc Renaudin

Yves Durand

Lionel Vincent

Olivier Debicki

Pascal Benoit

Philippe Maurine

Frédéric Heitzmann

Bettina Rebaud

Daniele Jahier Pagliari

Massimo Poncino

Yeter Akgul

Jérôme Quartana

Florent Berthier

Olivier Sentieys

Frederic Heitzmann

Christmann Jean-Frédéric

Daniele Jahier-Pagliari

This asynchronous processor core comprises a loading unit for sequentially loading instruction lines, functional units for executing instructions and a decoder for decoding instruction lines loaded by the loading unit into instructions executable by the functional units. It comprises an execution control module configured as a two-state automaton: a sleep state (S), wherein the asynchronous processor core awaits an interrupt control signal to execute an interrupt routine; an execution state (S), wherein the decoder awaits a new interrupt routine instruction line to be decoded. The execution control module additionally manages a state variable (status) of the loading unit to selectively authorize or prevent, according to at least the value of this state variable (status), the loading of a new instruction line.

Asynchronous core processor and a sensor node communication microcontroller including the same

The invention concerns a circuit comprising: a processing circuit () comprising a plurality of circuit domains (), each circuit domain () comprising a plurality of transistors and being configured to apply one or more corresponding transistor biasing voltages to said transistors; and a control circuit () configured to determine, based on at least a selected accuracy setting of the processing circuit, the level of said one or more transistor biasing voltages to be applied in each of said circuit domains, the control circuit () being further configured to cause said transistor biasing voltages to be applied to the circuit domains.

Processing circuit capable of dynamically modifying its precision

An asynchronous circuit including an asynchronous pipeline including two or more stages, each stage having: a buffering circuit for temporarily storing data to be transferred from one stage to the next based on a handshake protocol, the buffering circuit including a non-volatile memory; and a data presence detection circuit adapted to generate a data presence detection value indicating whether or not data is stored by the buffering circuit; and a control circuit adapted to perform a data back-up operation by independently controlling each buffering circuit to back-up the data it stores to its non-volatile memory based on the corresponding data presence detection value.

Data back-up in an asynchronous circuit

A method for controlling an electronic circuit by means of the first, second and third operating parameters, comprises: determining a range of variation of the third parameter for each value of the first parameter by varying the second parameter, said ranges being different; determining a target value of the third parameter; if the target value is within one of the ranges, operating the electronic circuit by setting the third parameter to the target value; and in the opposite case, selecting the two ranges framing the target value and operating the electronic circuit by consecutively bringing the third parameter into each one of the selected ranges.

Method for controlling an electronic circuit

The invention concerns a circuit comprising: a C-element having first and second input nodes and first and second inverters () cross-coupled between first and second complementary storage nodes (, Z), the second storage node (Z) forming an output node of the C-element; and a non-volatile memory comprising: a first resistive element () having a first terminal coupled to the first storage node (); a second resistive element () having a first terminal coupled to the second storage node (Z), at least one of the first and second resistive elements being programmable to have one of at least two resistive states (R, R), wherein a second terminal of the first resistive element () is coupled to a second terminal of the second resistive element () via a first transistor (); and a control circuit ().

C-element with non-volatile back-up

A device for powering an electronic circuit that applies at least a first voltage or a second voltage, different from the first voltage, to the electronic circuit. The device includes a performance monitor that receives an item of information defining a constraint and determines a first duration and a second duration, such that the operation of the electronic circuit at a first frequency associated with the first voltage for the first duration, and at a second frequency associated with the second voltage for the second duration, complies with the constraint. The device applies the first voltage and the first frequency to the circuit for the first duration and the second voltage and the second frequency for the second duration.

Device for powering an electronic circuit, in particular a digital circuit, and associated method

An electronic circuit power supply device configured to selectively apply at least one first voltage or one second voltage to a power supply terminal of the electronic circuit that includes elements for applying to the power supply terminal a voltage variable from a value equal to the first voltage to a value equal to the second voltage and elements designed for selecting application of the second voltage to the power supply terminal when the variable voltage reaches the second voltage.

Electronic circuit power supply device and electronic circuit

This invention relates to the domain of Networks on Chips (NoC) and relates to a method of transferring data in a network on chip, particularly using an asynchronous 'send/accept' type protocol. The invention also relates to a network on chip used to implement this method.

Globally asynchronous communication architecture for system on chip

A network and a data transmission method between elements in such a network using an asynchronous communication protocol of the 'send/accept' type. At least one node in the network operations without an internal clock, this node determining a transfer hierarchy between two data packets to be routed to the same output, at least as a function of a priority channel information associated with each data packet.

Communication node architecture in a globally asynchronous network on chip system

The invention concerns a radiation detection device comprising a plurality of detector elements (DET, DET), each detector element (DET) being associated with a circuit (AMP-CMP) for acquiring pulse signals (H) and for counting (CNT) detection events. The invention provides for means (COR) of correlating detection events corresponding to at least two detector elements (DET/DET).

Radiation detection system allowing improved counting of events

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Meaudre, France

Edith Beigne