Intersil Americas Inc.

Micro Linear Corporation

Edgardo A Laber

Alexander Kalnitsky

Michael D Church

Hosam Haggag

Yun Yue

Anthony John Allen

Prabhjot Singh

Bertram J Rodgers

Carlos Martinez

Systems and methods for an open wire scan are provided. In certain embodiments, An apparatus comprising a circuit includes a plurality of inputs for connecting with a plurality of outputs of a multi-cell battery pack; and an open connection detection circuit, formed within the circuit, for detecting an open connection on at least one of the plurality of inputs connected to the multi-cell battery pack and generating a fault condition responsive thereto. The open connection detection circuit comprises at least one current source device; and at least one device for turning on and off the at least one current source device. The open connection detection circuit also comprises at least one amplifier; an analog to digital converter; and a control logic circuit.

Systems and methods for an open wire scan

An apparatus comprises an integrated circuit and an open connection detection circuit within the integrated circuit. The integrated circuit includes a plurality of inputs for connecting with a plurality of outputs of a multi-cell battery pack. The open connection detection circuit within the integrated circuit detects an open connection on at least one of the plurality of inputs from the multi-cell battery and generates a fault condition responsive thereto.

System and method for detection of open connections between an integrated circuit and a multi-cell battery pack

A flash memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a floating gate memory transistor having a source region and a drain region, and a coupling capacitor electrically connected to the memory transistor. A plurality of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the drain region of the memory transistor in each of the memory cells in a respective column. A plurality of high voltage access transistors are each electrically connected to a bit line in the first set of bit lines. A second set of bit lines are each electrically connected to the source region of the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and the first and second sets of bit lines in operations to erase, program, inhibit, or read the logic state stored by the memory transistor in one or more of the memory cells.

Flash memory array of floating gate-based non-volatile memory cells

A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A first set of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A second set of word lines are each electrically connected to the access transistor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the access transistor in each of the memory cells in a respective column. A second set of bit lines are each electrically connected to the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and bit lines in operations to program, erase, read, or inhibit a logic state stored by the memory transistor in one or more of the memory cells.

Memory array of floating gate-based non-volatile memory cells

Circuits, methods, and apparatus that provide waveforms having controlled rise and fall times, as well as accurate peak voltages. One embodiment provides circuitry for generating a clock signal and a current that are adjusted for an on-chip capacitance variation. This current is then used to generate rising and falling edges of a waveform. The clock signal is used to determine timing of transitions in the waveform. A bandgap or similar reference voltage is used to determine the peak voltage. This waveform is then gained using an amplifier circuit, and the output of the amplifier circuit is used as a programming voltage waveform for an EE-PROM. One embodiment further uses non-overlapping clocks to drive a charge pump that is used to generate a supply voltage for the amplifier circuit that far exceeds the available on-chip supply voltages.

On-chip EE-PROM programming waveform generation

Circuit methods, and apparatus that provide waveforms having controlled rise and fall times, as well as accurate peak voltages. One embodiment provides circuitry for generating a clock signal and a current that are adjusted for an on-chip capacitance variation. This current is then used to generate rising and falling edges of a waveform. The clock signal is used to determine timing of transitions in the waveform. A bandgap or similar reference voltage is used to determine the peak voltage. This waveform is then gained using an amplifier circuit, and the output of the amplifier circuit is used as a programming voltage waveform for an EE-PROM. One embodiment further uses non-overlapping clocks to drive a charge pump that is used to generate a supply voltage for the amplifier circuit that far exceeds the available on-chip supply voltages.

A technique for interfacing transmission media in a local area network (LAN). A first transceiver and a second transceiver, each have a media dependent interface and a media independent interface. Each media dependent interface is coupled to respective transmission media while the media independent interfaces are coupled together. A receive clock output of the first transceiver is coupled to a first input of a first multiplexer. A receive clock output of the second transceiver is coupled to a first input of a second multiplexer. A fixed frequency clock signal is coupled to a second input of the first multiplexer and to a second input of the second multiplexer. An output of the first multiplexer is coupled to a reference clock input of the second transceiver. An output of the second multiplexer is coupled to a reference clock input of the first transceiver. A select input of the first multiplexer is coupled to a status output of the first transceiver. A select input of the second multiplexer is coupled to a status output of the second transceiver. The reference clock input for each transceiver is selectively coupled to the fixed-frequency clock signal or to the receive clock signal generated by the other transceiver according to whether data is being received from the other transceiver. Accordingly, data is passed from one transceiver to the other without intermediate buffering. Therefore, the invention reduces complexity associated with prior techniques for interfacing transmission media. Preferably, the invention is practiced in a Fast Ethernet LAN.

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Monte Sereno, CA, United States of America

Edgardo A Laber