United States of America as Represented by the Secretary of the Air Force

Edgar J Martinez

Michael Shur

Fritz L Schuermeyer

Charles L Cerny

This is a fabrication process for complementary III-V HFETs in which devices are built side-by-side in doped-areas, known as 'tubs', grown by molecular beam epitaxy on indium phosphide (InP) substrates, or other material systems such as materials grown on GaAs substrates. The layers grown are a semi-insulating buffer layer of InAlAs, a InGaAs channel, an InAlAs barrier layer and finally an InGaAs cap layer. All layers are lattice matched or pseudomorphic to the InP substrate. After mesa etching of areas around the transistor, a high temperature silicon nitride (Si.sub.3 N.sub.4) layer is deposited using chemical vapor deposition, and photoresist is deposited. Then n-well and p-well areas are formed in turn, with appropriate ion-implantation, stripping of the photoresist, and annealing to activate the dopants. Then the Si.sub.3 N.sub.4 is stripped and the samples thoroughly cleaned. Then, the refractory gate metal is sputtered, delineated with photoresist and reactive ion etch procedures. Areas for n-ohmic and p-ohmic contacts are formed, using with Si.sub.3 N.sub.4 and photoresist covering, ion implanting, and annealing. Finally the p- and n-ohmic contact metals are evaporated and alloyed. The typical n-ohmic metal system is Au/Ge/Ni while Au/Zn is used for the formation of the p-ohmic contacts. The integrated circuit is completed by depositing and patterning the interconnect metal.

Growing community of inventors

Spring Valley, OH, United States of America

Edgar J Martinez