Freescale Semiconductor,inc.

Edevaldo Pereira Silva, Jr

Ricardo Pureza Coimbra

Andre Luis Vilas Boas

Pedro Barbosa Zanetta

Ivan Carlos Ribeiro Nascimento

Eduardo Ribeiro Da Silva

Andre L Couto

In some embodiments, a source follower circuit may include a first level shifter configured to receive an input voltage; an N-type Metal-Oxide-Semiconductor (NMOS) transistor having a gate terminal coupled to an output of the first level shifter; a second level shifter configured to receive the input voltage; a P-type Metal-Oxide-Semiconductor (PMOS) transistor having a gate terminal coupled to an output of the second level shifter and a source terminal coupled to a source terminal of the NMOS transistor; and an amplifier configured to receive the input voltage and to output a current at a node between the source terminal of the NMOS transistor and the source terminal of the PMOS transistor, wherein the current is determined based upon a difference between the input voltage and a reference voltage.

Rail-to-rail follower circuits

Systems and methods for transition control in a hybrid Switched-Mode Power Supply (SMPS). In some embodiments, a hybrid SMPS may include linear circuitry configured to produce an output voltage proportional to a variable duty cycle when the SMPS operates in linear mode and hysteretic circuitry coupled to the linear circuitry, the hysteretic circuitry configured to cause the duty cycle to assume one of two predetermined values when the SMPS operates in hysteretic mode. The hybrid SMPS may also include transition circuitry coupled to the linear circuitry and to the hysteretic circuitry, the transition circuitry configured to bypass at least a portion of the linear circuitry in response to the hybrid SMPS transitioning from the hysteretic mode to the linear mode.

Transition control for a hybrid switched-mode power supply (SMPS)

Ready-flag circuitry for differential amplifiers. In some embodiments, a semiconductor device may include an amplifier including two inputs, and a ready-flag circuit operably coupled to the amplifier, the ready-flag circuit configured to monitor two or more internal nodes of the amplifier and to produce a signal indicating whether a voltage or current difference between the two inputs has been minimized. In other embodiments, a method may include monitoring, via a ready-flag circuit, a first and a second internal node of a differential amplifier, wherein the differential amplifier is part of a bandgap voltage reference circuit and producing, via the ready-flag circuit, a signal indicating whether an output of the bandgap voltage reference circuit has reached a nominal value.

Ready-flag circuitry for differential amplifiers

Metal-Oxide-Semiconductor (MOS) voltage divider with dynamic impedance control. In some embodiments, a voltage divider may include two or more voltage division cells, each voltage division cell having a plurality of Metal-Oxide-Semiconductor (MOS) transistors, a least one of the plurality of MOS transistors connected to a signal path and at least another one of the plurality of MOS transistors connected to a control path, the voltage division cell configured to provide a voltage drop across the signal path based upon a control signal applied to the control path.

Growing community of inventors

Campinas, Brazil

Edevaldo Pereira Silva, Jr