Texas Instruments Corporation

Micron Technology Incorporated

Other

Eden M Zielinski

Zhiping Yin

Fred D Fishburn

Girish Anant Dixit

Kenneth D Brennan

David Brian Aldrich

Peter S McAnally

Scott Robert Summerfelt

Robert H Havemann

Jeffrey Alan West

Qi-Zhong Hong

Scott David Johnson

Manoj K Jain

Patricia Beauregard Smith

Ping Jiang

Guoqiang Xing

Ted S Moise

Karen H R Kirmse

Stephen W Russell

Rob Kraft

Methods are disclosed for forming trench or via cavities in a single damascene interconnect structure, comprising etching a dielectric layer to form a cavity there and to expose an underlying etch-stop layer, and etching the exposed etch-stop layer to extend the cavity and to expose a conductive feature in an existing interconnect structure, wherein etching the portion of the dielectric layer and etching the exposed portion of the etch-stop layer are performed concurrently with substantially no intervening processing steps therebetween. Also disclosed are methods of forming a via cavity in a dual damascene interconnect structure, comprising forming an etch-stop layer over an existing interconnect structure, forming a dielectric layer over the etch-stop layer, etching a portion of the dielectric layer to form a via cavity in the dielectric layer and to expose a portion of the etch-stop layer, and etching the etch-stop layer to extend the via cavity, where the dielectric layer is covered during etching of the etch-stop layer.

Methods for forming single damascene via or trench cavities and for forming dual damascene via cavities

A method of depositing a non-conductive barrier layer onto a metal surface wherein the resistance of the metal remains substantially unchanged before and after the non-conductive barrier layer deposition. The deposition process provides a low temperature processing environment so as to inhibit the formation of impurities such as silicide in the metal, wherein the silicide can adversely increase the resistance of the underlying metal.

Low temperature nitride used as Cu barrier layer

Integrated circuit structures comprising an embedded ferroelectric memory cell and methods of forming the same are described. These structures include a transistor level, a ferroelectric device level, a first metal level, an inter-level dielectric level and a second metal level. In a first embodiment, the ferroelectric device level is disposed over an isolation layer of the transistor level and an isolation layer of the ferroelectric level has one or more vias that are laterally sized larger than corresponding contact vias extending through the transistor isolation layer and aligned therewith. In a second embodiment, the first metal level and the ferroelectric device level are integrated into the same level. In a third embodiment, the ferroelectric device level is disposed over the first metal level. In a fourth embodiment, the ferroelectric device level is disposed over the inter-level dielectric level that, in turn, is disposed over the first metal level. In a fifth embodiment, the ferroelectric device level is disposed over the transistor isolation layer and the ferroelectric isolation layer has one or more vias extending through the ferroelectric isolation layer and the transistor isolation layer. These embodiments implement different strategies for improving the yield and performance of embedded ferroelectric devices.

Fabricating an embedded ferroelectric memory cell

A dual inlaid interconnect fabrication method using a temporary filler in a via during trench etch and removal of the filler after trench etch. This provides via bottom protection during trench etch.

Integrated circuit interconnect and method

An embodiment of the instant invention is a method of forming an electronic device over a semiconductor substrate and having at least one level of metallic conductors, the method comprising the steps of: forming a dielectric layer over the semiconductor substrate, the dielectric layer having openings (step,of FIG.,); forming a layer of the metallic conductor on the dielectric layer (step,of FIG.,); removing a portion of the layer of the metallic conductor on the dielectric layer (step,of FIG.,); and subjecting the exposed metallic conductor to a plasma which contains hydrogen or deuterium so as to passivate the metallic conductor (step,of FIG.,). Preferably, the plasma contains a substance selected from the group consisting of: NH,, N,H,, H,S, and CH,, and the metallic conductors are comprised of a material selected from the group consisting of: copper, copper doped aluminum, Ag, Sn, Pb, Ti, Cr, Mg, Ta, and any combination thereof. The step of removing a portion of the layer of the metallic conductor is, preferably, performed by sputtering off a portion of the metallic conductor, chemical-mechanical polishing, etching, or a combination thereof.

Hydrogen passivation of chemical-mechanically polished copper-containing layers

A structure and method to direct the via,etch to the top of the interconnect,by using a sidewall layer,preferably. TiN, and thus preventing the etching down the side of the interconnect,and exposure of materials residing between the interconnects

Sidewalls for guiding the via etch

A structure and method to direct the via 270 etch to the top of the interconnect 210, by using a sidewall layer 240, preferably TiN, and thus preventing the etching down the side of the interconnect 210 and exposure of materials residing between the interconnects 210.

Growing community of inventors

Rowlett, TX, United States of America

Eden M Zielinski