Fairchild Semiconductor Corporation

Siliconix Incorporated

National Semiconductor Corporation

Eddy Tjhia

Chung-Lin Wu

James J Murphy

Michael D Gruenhagen

Suku Kim

Mark Larsen

Oseob Jeon

Frank Kuo

Bigildis Dosdos

Douglas E Dolan

Yehja Mohammed Kasem

Anup Bhalla

Yueh-Se Ho

Jacek Korec

Y Mohammed Kasem

Ihsiu Ho

Bosco Lan

Chang-Sheng Chen

Rohit Dikshit

Lee Shawn Luo

Anjali Anagol-Subbarao

Chi Lin

Disclosed are semiconductor dice with backside trenches filled with elastic conductive material. The trenches reduce the on-state resistances of the devices incorporated on the dice. The elastic conductive material provides a conductive path to the backsides of the die with little induced stress on the semiconductor die caused by thermal cycling. Also disclosed are packages using the dice, and methods of making the dice.

Semiconductor dice with backside trenches filled with elastic material for improved attachment, packages using the same, and methods of making the same

An exemplary semiconductor die package of the invention has a metal-oxide substrate disposed between a first surface of a semiconductor die and a heat-sinking component, with a conductive die clip or one or more electrical interconnect traces disposed between the metal-oxide substrate and the first surface of the semiconductor die. The heat-sinking component may comprise a heat sink, or an adaptor plate to which a heat sink may be coupled. The conductive die clip or electrical trace(s) provides electrical connection(s) to the first surface of the semiconductor die, while the metal-oxide substrate electrically insulates the die from the heat-sinking component, and provides a path of high thermal conductivity between the die and the heat-sinking component. The second surface of the semiconductor die may be left free to connect to a circuit board, or a leadframe or interconnect substrate may be attached to it.

High-power semiconductor die packages with integrated heat-sink capability and methods of manufacturing the same

Disclosed are semiconductor die structures that enable a die having a vertical power device to be packaged in a wafer-level chip scale package where the current-conducting terminals are present at one surface of the die, and where the device has very low on-state resistance. In an exemplary embodiment, a trench and an aperture are formed in a backside of a die, with the aperture contacting a conductive region at the top surface of the die. A conductive layer and/or a conductive body may be disposed on the trench and aperture to electrically couple the backside current-conducting electrode of the device to the conductive region. Also disclosed are packages and systems using a die with a die structure according to the invention, and methods of making dice with a die structure according to the invention.

Semiconductor die structures for wafer-level chipscale packaging of power devices, packages and systems for using the same, and methods of making the same

Semiconductor chip package

In a semiconductor package for a chip having terminals on both sides, for example, a power MOSFET in which the gate and source terminals are on the front side and the drain terminal is on the back side, electrical contact is made with the back side terminal by extending vias, which can take the form of trenches, holes or other cavities, either entirely or patrially through the chip. The vias are filled with a metal or other electrically conductive material. The process is performed on the chips in a wafer simultaneously. The resulting package is compact and economical to manufacture and can readily be mounted, flip-chip style, on a printed circuit board.

Vertical structure for semiconductor wafer-level chip scale packages

A photolithographic process for forming a lead frame pattern or other pattern is described. In the preferred embodiment, a mask approximately 12 inches by 12 inches contains two nearly identical patterns: a first lead frame pattern is provided on one half of the mask, and a second lead frame pattern, having features reduced by 0.3 mil, is provided on the other half of the mask. The first pattern is positioned over a copper web having a layer of photoresist laminated on it, and ultraviolet light is transmitted through the first pattern. The photoresist is thus exposed by a first image formed by the first pattern. While the copper web remains stationary, the mask is moved perpendicular to the length of the copper web so that the second pattern now forms a second image overlying the photoresist pattern from the first image. The photoresist layer is then exposed by the second image. The two nearly identical patterns on the mask essentially double expose the photoresist except for a 0.3 mil edge around all features, so that particles on either of the mask patterns will not significantly affect the final lead frame pattern formed in the photoresist. By not requiring the copper web to be moved during this process, the overlapping lead frame patterns can be aligned much more precisely by shifting the mask rather than by shifting the copper web.

Photolithographic process for reducing repeated defects

Growing community of inventors

Sunnyvale, CA, United States of America

Eddy Tjhia