International Business Machines Corporation

Eddy St Juste

Christopher J Berry

Shyam Ramji

Randall J Darden

Matthew D Affeldt

Sourav Saha

Timothy A Schell

Joseph J Palumbo

David L Rude

Christopher Carney

Adam R Jatkowski

Michael Romain

Aspects of the invention include a method that includes performing timing analysis of an integrated circuit design to identify a critical path. The critical path fails to meet a corresponding timing requirement. The method also includes determining an amount of slack needed by the critical path. The amount of slack is an amount by which the critical path fails to meet the corresponding timing requirement. Downstream slack is created in each path of a next cycle, wherein each path of the next cycle is immediately downstream of the critical path. Slack stealing is performed to improve timing of the critical path based on the downstream slack created in each path of the next cycle.

Downstream slack creation in integrated circuit development

A system and a computer implemented method for interior pinning in a macro block of an integrated circuit are provided. The method includes receiving child level information of the macro block including at least a location of a logic leaflet, receiving parent level information including at least edge direction information for pin connection and routing resource values of each slot of the macro block at each metal layer, and selecting a pin location based on the child level information and the parent level information.

Hierarchically aware interior pinning for large synthesis blocks

A computer-implemented method of performing physical synthesis in a chip design process using hierarchical wire-pin co-optimization, a system, and a computer program product are described. Aspects include providing an indication of candidate pins among a plurality of pins of a plurality of macros that may be moved, and providing constraints on a range of movement of one or more of the plurality of pins. Aspects also include performing macro-level physical synthesis at each of the plurality of macros based on the candidate pins and the constraints to generate pin locations and timing results.

Constraint-driven pin optimization for hierarchical design convergence

In a hierarchical semiconductor digital unit comprised of a plurality of macro functional logic blocks, each of said macro functional logic blocks comprised of a plurality of leaf cells, each of said leaf cells accessed via an input terminal and an output terminal, the improvement wherein locating each input terminal provides access to a single leaf cell at a legal location proximate the leaf cell to which the input terminal provides access.

Semi-flattened pin optimization process for hierarchical physical designs

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Bridgeport, CT, United States of America

Eddy St Juste