U.S. Philips Corporation

Eddy A Odijk

Eduard Ferdinand Stikvoort

Eric H Persoon

Henricus A Van Gestel

Christian J Vandenbulcke

Rogatus H Wester

Franciscus P Hopmans

Robert A Van Twist

Johannis M Jansen

A television receiver includes a teletext decoder which is adapted to check whether a keyword entered by the user occurs in a teletext cycle. The teletext pages with the searched keyword, or their page numbers, are identified and stored for later display or selection. The receiver has arrow keys for selecting the keyword on the display screen so that an alphabetical keyboard is not necessary. The receiver also includes a non-volatile memory in which a personal index of keywords can be programmed.

Teletext decoder and television receiver provided with a teletext decoder

A description is given of a data processing network that is constructed as a product network of two or more factor networks. At least one of the factor networks is a chordal ring of at least five stations, or a generalized chordal ring. A generalized chordal ring is formed by dividing each of the stations in a chordal ring (124, 130, 136) into a number of sub-stations. The sub-stations within a station constitute a homogeneous network. The external connections of a station are divided over the relevant sub-stations. In this way an optimum value for the degree (G) and diameter (D) of the network can be chosen on the basis of a selection strategy.

A data processing network with chordal ring factor network

A random access memory is used to realize a sequence of delay lines (40, 46, 48, 50). The delay lines are linked so that a common end point of two delay lines can be addressed in a read/modify/write operation. Furthermore, the address step between two successive data elements of the delay line is increased, so that the new address must be calculated modulo the length of the consecutive zone reserved for the delay lines. It has been found that in many cases the incrementation step between the various read addresses has a value which can be expressed in a number of bits which is smaller than the number of bits necessary to express the length of the consecutive memory zone itself.

Method of addressing a random access memory as a delay line, and signal

An integrated data processor which includes a multiplier element provided with non-symmetrical operand inputs and an arithmetic and logic unit which is connected to the output of the multiplier element by way of a connection over the full product width. The ALU also comprises an accumulator device. Multiple-precision operations can thus be performed on the quantities received on each of the two inputs of the multiplier element. The data processor is notably suitable for performing each time identical operations on sequentially arriving signal quantities.

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Eindhoven, Netherlands

Eddy A Odijk