Agilent Technologies, Inc.

Hewlett-packard Company

Eddie L Williamson

Myron J Schneider

David T Crook

Stephen P Rozum

Steven K List

Tak Yee Kwan

A method for verifying the integrity of the electrical connection between at least one signal path of a substrate and at least one respective contact of a component mounted on the substrate is disclosed. The method includes generating a step signal on one of the at least one signal path connected to a respective contact, and capturing a capacitively coupled signal due to the step signal at the contact. The method further includes determining the integrity of the electrical connection from a characteristic of the capacitively coupled signal or a response signal obtained from the capacitively coupled signal. A tester in which the method is implemented is also disclosed.

Method and tester for verifying the electrical connection integrity of a component to a substrate

Capacitive leadframe testing techniques are improved through knowledge of characteristics of semiconductor junctions specific to nodes of device under test (DUT) that are connected to nodes under test of the DUT.

Method for using internal semiconductor junctions to aid in non-contact testing

The present invention is a method an apparatus for diagnosing short defects on inaccessible or non-contacted nodes of an integrated circuit device using capacitive coupling techniques. In accordance with the invention, an alternating current (AC) signal generator is connected to apply an alternating current (AC) signal to an accessible node of an IC device under test. Preferably, all remaining accessible nodes of the IC device under test are grounded. A sensor plate of a capacitive sensing probe is placed in signal coupling proximity to the inaccessible node of interest on the integrated circuit device. If a signal is present on the inaccessible node of interest, it is capacitively coupled to the sensor plate of the probe. A measurement device obtains a measurement representative of an amount of current flow capacitively coupled to the sensor plate by the capacitive sensing probe. The possible existence of a short defect between the stimulated accessible node and the inaccessible node can be inferred based on the measurement and/or on a parameter derived from the measurement.

Method and apparatus for detecting shorts on inaccessible pins using capacitive measurements

A method and apparatus for diagnosing open defects on non-contacted nodes of an electrical device is presented. Actual and expected signal measurements are collected for various contacted nodes of the electrical device. Nodes whose actual measurements are out of range of their respective expected measurements are deemed abnormal nodes. Non-contacted nodes may then be assessed as having, or as likely to have, open defects based on knowledge of the degree of coupling of the non-contacted node to the abnormal contacted nodes. In the preferred embodiment, abnormal nodes are identified using a linear regression analysis, and the non-contacted nodes indicted as having open defects are identified using a weighting scheme.

Method for diagnosing open defects on non-contacted nodes of an electronic device from measurements of capacitively coupled nodes

A method and system is presented for optimizing the number of required measurements to obtain in real-time by an automated tester that tests a device under test. During a test run, historical measurements are obtained and tracked. Each subsequent iteration the test attempts to re-measure the fewest number of measurements in real-time to obtain an accurate reflection of whether the device being tested passes or fails based on the real-time measurements and substituting historical measurements for those required measurements that were not taken in real-time.

Method and apparatus for adaptively learning test error sources to reduce the total number of test measurements required in real-time

The system is for testing semiconductor components such as TTL components and CMOS components to determine whether the input, output and ground pins are conductively connected to a circuit, such as the circuit of a printed circuit board, and whether proper conductive paths exist between the connector pins and the ground pin through the semiconductor. This is accomplished by providing a current pulse on one terminal to generate a voltage drop across an inherent resistance of the component which is connected in series with the other terminal of the component and detecting the resulting voltage drop. The existence of the voltage drop indicates that both the input and output terminals, as well as the ground terminal, are properly connected to the printed circuit board.

Integrated circuit transfer test device system

A system and method for unambiguously determining the orientation of a semiconductor component in a circuit. The invention draws a predetermined biasing current from the signal node of a circuit that is sufficient to forward bias protection and/or parasitic diodes that exist between the ground pin and signal pin of the semiconductor component. Hence, if all of the semiconductors coupled to a signal node are connected in proper orientation, a voltage of -V.sub.D will be detected on the signal node. A voltage of approximately two diode voltage drops is applied to the power node so that the protection and/or parasitic diodes of a semiconductor placed in the circuit in reverse orientation will be forward biased to produce a voltage on the signal node equal to approximately one diode voltage drop. Missing components and bent pins do not affect the results of the test performed by the present invention. Guarding techniques on the signal node are not required since impedances coupled to the signal node are normally high enough to allow the protection and/or parasitic diodes to be forward biased by current supplied by the current source.

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Fort Collins, CO, United States of America

Eddie L Williamson